Semiconductor device

ABSTRACT

A semiconductor device having high on-state current and favorable reliability is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a first conductor over the third oxide; a second conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a third conductor positioned over the second insulator and overlapping with the second oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide, and the conductivity of the fourth oxide is higher than the conductivity of the second oxide.

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. It can be sometimes said that a display device (a liquid crystal display device, a light-emitting display device, and the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, and the like include a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Another embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.

BACKGROUND ART

A silicon-based semiconductor material is widely known as a semiconductor thin film that can be used in a transistor, and as another material, an oxide semiconductor has attracted attention. As the oxide semiconductor, not only single-component metal oxides, such as indium oxide and zinc oxide, but also multi-component metal oxides are known. Among the multi-component metal oxides, in particular, an In—Ga—Zn oxide (hereinafter also referred to as IGZO) has been actively studied.

From the studies on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are not single crystal nor amorphous, have been found in an oxide semiconductor (see Non-Patent Document 1 to Non-Patent Document 3). In Non-Patent Document 1 and Non-Patent Document 2, a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure is also disclosed. Moreover, Non-Patent Document 4 and Non-Patent Document 5 show that a fine crystal is included even in an oxide semiconductor which has lower crystallinity than an oxide semiconductor having the CAAC structure or the nc structure.

In addition, a transistor that uses IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and an LSI and a display utilizing the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8).

PRIOR ART DOCUMENTS Non-Patent Documents

-   [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of     Technical Papers”, 2012, volume 43, issue 1, p. 183-186. -   [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of     Applied Physics”, 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10. -   [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13     Digest of Technical Papers”, 2013, p. 151-154. -   [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid     State Science and Technology”, 2014, volume 3, issue 9, p.     Q3012-Q3022. -   [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”, 2014,     volume 64, issue 10, p. 155-164. -   [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied     Physics”, 2012, volume 51, p. 021201-1-021201-7. -   [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI     Technology Digest of Technical Papers”, 2015, p. T216-T217. -   [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of     Technical Papers”, 2010, volume 41, issue 1, p. 626-629.

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

An object of one embodiment of the present invention is to provide a semiconductor device having a high on-state current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having excellent frequency characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having favorable reliability. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long time. An object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed data writing. An object of one embodiment of the present invention is to provide a semiconductor device having high design flexibility. An object of one embodiment of the present invention is to provide a semiconductor device in which power consumption can be reduced. An object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of these objects does not preclude the existence of other objects. Note that one embodiment of the present invention does not necessarily achieve all of these objects. Objects other than these will be apparent from the description of the specification, the drawings, the claims, and the like, and objects other than these can be derived from the description of the specification, the drawings, the claims, and the like.

Means for Solving the Problems

One embodiment of the present invention is a semiconductor device including a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor positioned over the second insulator and overlapping with the second oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The conductivity of the fourth oxide is higher than the conductivity of the second oxide.

One embodiment of the present invention is a semiconductor device including a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor positioned over the second insulator and overlapping with the second oxide. The third oxide comprises a first region not overlapping with the first conductor. The fourth oxide comprises a second region not overlapping with the second conductor. The fifth oxide is in contact with each of a top surface of the first region and a top surface of the second region. The conductivity of the third oxide is higher than the conductivity of the second oxide. The conductivity of the fourth oxide is higher than the conductivity of the second oxide.

Each of the third oxide and the fourth oxide preferably contains zinc. Each of the third oxide and the fourth oxide preferably has crystallinity.

The thickness of each of the third oxide and the fourth oxide is preferably greater than or equal to 1 nm and less than or equal to 10 nm.

The thickness of each of the third oxide and the fourth oxide may be greater than or equal to 1 nm and less than or equal to 5 nm.

The second oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.

Effect of the Invention

According to one embodiment of the present invention, a semiconductor device having a high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having excellent frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high productivity can be provided.

Alternatively, a semiconductor device capable of retaining data for a long time can be provided. Alternatively, a semiconductor device capable of high-speed data writing can be provided. Alternatively, a semiconductor device with high design flexibility can be provided. Alternatively, a semiconductor device in which power consumption can be reduced can be provided. Alternatively, a novel semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Effects other than these will be apparent from the description of the specification, the drawings, the claims, and the like, and effects other than these can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (A) A top view illustrating a structure example of a semiconductor device. (B), (C) A cross-sectional view illustrating a structure example of a semiconductor device.

FIG. 2 (A) A top view illustrating a structure example of a semiconductor device. (B), (C) A cross-sectional view illustrating a structure example of a semiconductor device.

FIG. 3 Cross-sectional views each illustrating a structure example of a semiconductor device.

FIG. 4 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 5 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 6 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 7 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 8 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 9 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 10 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 11 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 12 A diagram illustrating an energy band structure of an oxide semiconductor.

FIG. 13 (A) A top view illustrating a structure example of a semiconductor device. (B), (C) A cross-sectional view illustrating a structure example of a semiconductor device.

FIG. 14 (A) A top view illustrating a structure example of a semiconductor device. (B), (C) A cross-sectional view illustrating a structure example of a semiconductor device.

FIG. 15 A cross-sectional view illustrating a structure example of a semiconductor device.

FIG. 16 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 17 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 18 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 19 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 20 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 21 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 22 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 23 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 24 (A) A top view illustrating a method of manufacturing a semiconductor device. (B), (C) A cross-sectional view illustrating a method of manufacturing a semiconductor device.

FIG. 25 A cross-sectional view illustrating a structure example of a memory device.

FIG. 26 A cross-sectional view illustrating a structure example of a memory device.

FIG. 27 A cross-sectional view illustrating a structure example of a memory device.

FIG. 28 A cross-sectional view illustrating a structure example of a memory device.

FIG. 29 (A) A block diagram illustrating a structure example of a memory device. (B) A perspective view illustrating a structure example of a memory device.

FIG. 30 (A), (B), (C), (D), (E), (F), (G), (H) A circuit diagram illustrating a structure example of a memory device.

FIG. 31 (A) A block diagram illustrating a structure example of a semiconductor device. (B) A perspective view illustrating a structure example of a semiconductor device.

FIG. 32 (A), (B), (C), (D), (E) A schematic diagram illustrating a structure example of a memory device.

FIG. 33 A view illustrating a product image that can be used for a semiconductor device.

FIG. 34 (A), (B), (C), (D), (E1), (E2), (F) A diagram illustrating an electronic device.

FIG. 35 A graph showing measurement results of sheet resistances in Example.

FIG. 36 (A), (B), (C), (D), (E), (F) A cross-sectional TEM image showing an electron diffraction pattern in Example.

FIG. 37 (A), (B), (C), (D), (E), (F) A cross-sectional TEM image showing an electron diffraction pattern in Example.

FIG. 38 (A), (B), (C), (D), (E), (F) A cross-sectional TEM image of a region subjected to elementary analysis, which shows proportions of elements in the depth direction.

FIG. 39 (A), (B), (C), (D), (E), (F) A cross-sectional TEM image of a region subjected to elementary analysis, which shows proportions of elements in the depth direction.

FIG. 40 (A), (B) A graph showing XPS measurement results in Example.

FIG. 41 (A) A graph showing a spectrum obtained by XPS measurement in Example. (B) A graph showing XPS measurement results in Example.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments will be described with reference to drawings. However, the embodiments can be implemented with many different modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope thereof. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, the size, the layer thickness, or the region is not limited to the scale. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes, values, or the like shown in the drawings. For example, in the actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which is not reflected in the drawings in some cases for easy understanding. Note that in drawings, the same reference numerals are used, in different drawings, for the same portions or portions having similar functions, and repeated description thereof is omitted in some cases. Furthermore, the same hatch pattern is used for the portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.

Furthermore, especially in a top view (also referred to as a “plan view”), a perspective view, or the like, the description of some components might be omitted for easy understanding of the invention. Furthermore, the description of some hidden lines and the like might be omitted.

Note that in this specification and the like, the ordinal numbers such as first and second are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, description can be made even when “first” is replaced with “second”, “third”, or the like, as appropriate. In addition, the ordinal numbers in this specification and the like do not correspond to the ordinal numbers which are used to specify one embodiment of the present invention in some cases.

In this specification and the like, terms for describing arrangement, such as “over” and “under”, are used for convenience in describing a positional relationship between components with reference to drawings. Furthermore, the positional relationship between components is changed as appropriate in accordance with a direction in which each component is described. Thus, without limitation to terms described in this specification, the description can be changed appropriately depending on the situation.

In the case where there is an explicit description, X and Y are connected, in this specification and the like, for example, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are disclosed in this specification and the like. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, a connection relationship other than one shown in drawings or texts is disclosed in the drawings or the texts.

Here, X and Y denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Functions of a source and a drain might be switched when a transistor of opposite polarity is employed or a direction of current is changed in circuit operation. Therefore, the terms “source” and “drain” can be interchanged with each other in this specification and the like in some cases.

Note that in this specification and the like, depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter, referred to as an “effective channel width”) is different from a channel width shown in a top view of a transistor (hereinafter, referred to as an “apparent channel width”) in some cases. For example, when a gate electrode covers a side surface of a semiconductor, an effective channel width is greater than an apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a gate electrode covering a side surface of a semiconductor, the proportion of a channel formation region formed in the side surface of the semiconductor is increased in some cases. In that case, an effective channel width is greater than an apparent channel width.

In such a case, an effective channel width is difficult to estimate by actual measurement in some cases. For example, estimation of an effective channel width from a design value requires an assumption that the shape of a semiconductor is known. Accordingly, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately.

In this specification, the simple term “channel width” refers to an apparent channel width in some cases. Alternatively, in this specification, the simple term “channel width” refers to an effective channel width in some cases. Note that values of a channel length, a channel width, an effective channel width, an apparent channel width, and the like can be determined, for example, by analyzing a cross-sectional TEM image and the like.

Note that an impurity in a semiconductor refers to, for example, elements other than the main components of a semiconductor. For example, an element with a concentration of lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, for example, DOS (Density of States) in a semiconductor may be increased or the crystallinity may be decreased. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor; hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen are given as examples. In the case of an oxide semiconductor, water also functions as an impurity in some cases. In addition, in the case of an oxide semiconductor, oxygen vacancies are formed by mixing of impurities in some cases. Furthermore, in the case where the semiconductor is silicon, examples of an impurity which changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

Note that in this specification and the like, a silicon oxynitride film is a film in which oxygen content is higher than nitrogen content in its composition. Moreover, a silicon nitride oxide film is a film in which nitrogen content is higher than oxygen content in its composition.

In addition, in this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. Moreover, the term “conductor” can be replaced with a conductive film or a conductive layer. Furthermore, the term “semiconductor” can be replaced with a semiconductor film or a semiconductor layer.

In this specification and the like, the term “parallel” indicates a state where two straight lines are placed such that the angle formed therebetween is greater than or equal to −10° and less than or equal to 10°. Thus, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. Furthermore, the term “substantially parallel” indicates a state where two straight lines are placed such that the angle formed therebetween is greater than or equal to −30° and less than or equal to 30°. Moreover, “perpendicular” indicates a state where two straight lines are placed such that the angle formed therebetween is greater than or equal to 80° and less than or equal to 100°. Thus, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. In addition, “substantially perpendicular” indicates a state where two straight lines are placed such that the angle formed therebetween is greater than or equal to 60° and less than or equal to 120°.

Note that in this specification, a barrier film means a film having a function of inhibiting transmission of impurities and impurities such as water and hydrogen, and the barrier film having conductivity is referred to as a conductive barrier film in some cases.

In this specification and the like, a metal oxide is an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, in the case where a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. That is, in the case where an OS FET or an OS transistor is stated, it can also be referred to as a transistor including an oxide or an oxide semiconductor.

In this specification and the like, the term of normally off means that current per micrometer of channel width flowing through a transistor when no potential is applied to a gate or the gate is supplied with a ground potential is 1×10⁻²⁰ A or lower at room temperature, 1×10⁻¹⁸ A or lower at 85° C., or 1×10⁻¹⁶ A or lower at 125° C.

Embodiment 1

An example of a semiconductor device including a transistor 200 of one embodiment of the present invention is described below.

Structure Example of Semiconductor Device

FIGS. 1(A), 1(B), and 1(C) are a top view and cross-sectional views of the transistor 200 of one embodiment of the present invention and the periphery of the transistor 200.

FIG. 1(A) is a top view of the semiconductor device including the transistor 200. FIGS. 1(B) and 1(C) are cross-sectional views of the semiconductor device. Here, FIG. 1(B) is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in FIG. 1(A), and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1(C) is a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4 in FIG. 1(A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 1(A).

The semiconductor device of one embodiment of the present invention includes an insulator 214 over a substrate (not illustrated), the transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 274 over the insulator 282, and an insulator 281 over the insulator 274. The insulator 214, the insulator 280, the insulator 282, the insulator 274, and the insulator 281 function as interlayer films. A conductor 240 (a conductor 240 a and a conductor 240 b) that functions as a plug and is electrically connected to the transistor 200 is also included. Note that an insulator 241 (an insulator 241 a and an insulator 241 b) is provided in contact with a side surface of the conductor 240 functioning as a plug. A conductor 246 (a conductor 246 a and a conductor 246 b) electrically connected to the conductor 240 and functioning as a wiring is provided over the insulator 281 and the conductor 240.

The insulator 241 a is provided in contact with the inner wall of an opening in an insulator 272, an insulator 273, the insulator 280, the insulator 282, the insulator 274, and the insulator 281, a first conductor of the conductor 240 a is provided in contact with the side surface of the insulator 241 a, and a second conductor of the conductor 240 a is provided on the inner side thereof. The insulator 241 b is provided in contact with the inner wall of an opening in the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 274, and the insulator 281, a first conductor of the conductor 240 b is provided in contact with the side surface of the insulator 241 b, and a second conductor of the conductor 240 b is provided on the inner side thereof. Here, a top surface of the conductor 240 and a top surface of the insulator 281 can be substantially level with each other. Note that although the transistor 200 having a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is illustrated, the present invention is not limited thereto. For example, the conductor 240 may be provided as a single layer or to have a stacked-layer structure of three or more layers. When a component has a stacked-layer structure, layers may be distinguished by ordinal numbers corresponding to the formation order.

[Transistor 200]

As illustrated in FIG. 1, the transistor 200 includes an insulator 216 over the insulator 214; a conductor 205 (a conductor 205 a and a conductor 205 b) disposed so as to be embedded in the insulator 216; an insulator 222 over the insulator 216 and the conductor 205; an insulator 224 over the insulator 222; an oxide 230 a over the insulator 224; an oxide 230 b over the oxide 230 a; an oxide 243 a and an oxide 243 b over the oxide 230 b; a conductor 242 a over the oxide 243 a; a conductor 242 b over the oxide 243 b; an oxide 230 c over the oxide 230 b; an insulator 250 over the oxide 230 c; a conductor 260 (a conductor 260 a and a conductor 260 b) positioned over the insulator 250 and overlapping with the oxide 230 c; an insulator 272 in contact with part of a top surface of the insulator 224, a side surface of the oxide 230 a, a side surface of the oxide 230 b, a side surface of the oxide 243 a, a side surface of the oxide 243 b, a side surface of the conductor 242 a, a top surface of the conductor 242 a, a side surface of the conductor 242 b, and a top surface of the conductor 242 b; and an insulator 273 over the insulator 272. The oxide 230 c is in contact with a side surface of the oxide 243 a and a side surface of the oxide 243 b. The conductor 260 includes the conductor 260 a and the conductor 260 b, and the conductor 260 a is positioned so as to cover a bottom surface and a side surface of the conductor 260 b. Here, as illustrated in FIG. 1(B), a top surface of the conductor 260 is disposed to be substantially aligned with a top surface of the insulator 250 and a top surface of the oxide 230 c. The insulator 282 is in contact with a top surface of each of the conductor 260, the oxide 230 c, the insulator 250, and the insulator 280.

It is preferable that the insulator 222, the insulator 272, the insulator 273, and the insulator 282 have a function of inhibiting diffusion of hydrogen (e.g., at least one of a hydrogen atom, a hydrogen molecule, and the like). In addition, it is preferable that the insulator 222, the insulator 272, the insulator 273, and the insulator 282 have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). For example, the insulator 222, the insulator 272, the insulator 273, and the insulator 282 each preferably have a lower permeability of one or both of oxygen and hydrogen than the insulator 224. The insulator 222, the insulator 272, the insulator 273, and the insulator 282 each preferably have a lower permeability of one or both of oxygen and hydrogen than the insulator 250. The insulator 222, the insulator 272, the insulator 273, and the insulator 282 each preferably have a lower permeability of one or both of oxygen and hydrogen than the insulator 280.

As illustrated in FIG. 1(B), the insulator 272 is preferably in contact with the top and side surfaces of the conductor 242 a, the top and side surfaces of the conductor 242 b, the side surface of the oxide 243 a, the side surface of the oxide 243 b, the side surface of the oxide 230 a, the side surface of the oxide 230 b, and the top surface of the insulator 224. The insulator 273 is preferably provided over and in contact with the insulator 272. Thus, the insulator 280 is isolated from the insulator 224 and the oxide 230 by the insulator 272 and the insulator 273.

The oxide 230 preferably includes the oxide 230 a over the insulator 224, the oxide 230 b over the oxide 230 a, and the oxide 230 c which is placed over the oxide 230 b and at least partly in contact with a top surface of the oxide 230 b.

The transistor 200 has, in the region where a channel is formed (hereinafter also referred to as a channel formation region) and its vicinity, a structure in which three layers of the oxide 230 a, the oxide 230 b, and the oxide 230 c are stacked; however, the present invention is not limited thereto. For example, a structure may be employed in which a single-layer structure of the oxide 230 b, a two-layer structure of the oxide 230 b and the oxide 230 a, a two-layer structure of the oxide 230 b and the oxide 230 c, or a stacked-layer structure of four or more layers is provided. Although the transistor 200 with a structure in which the conductor 260 has a stacked-layer structure of two layers is described, the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked-layer structure of three or more layers.

Here, the conductor 260 functions as a gate electrode of the transistor and the conductor 242 a and the conductor 242 b function as a source electrode and a drain electrode. In the transistor 200, the conductor 260 functioning as the gate electrode is formed in a self-aligned manner to fill an opening formed in the insulator 280 and the like. The formation of the conductor 260 in this manner allows the conductor 260 to be surely placed in a region between the conductor 242 a and the conductor 242 b without alignment.

In the transistor 200, as the oxide 230 (the oxide 230 a, the oxide 230 b, and the oxide 230 c), which includes a channel formation region, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.

The transistor 200 using an oxide semiconductor in a channel formation region has an extremely low leakage current (off-state current) in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be deposited by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.

For example, as the oxide 230, a metal oxide such as an In-M-Zn oxide (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M Furthermore, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

A transistor using an oxide semiconductor is likely to have its electrical characteristics changed when impurities and oxygen vacancies exist in a region of the oxide semiconductor where a channel is formed, which may affect the reliability. Moreover, if the region of the oxide semiconductor where a channel is formed includes oxygen vacancies, the transistor tends to have normally-on characteristics. Therefore oxygen vacancies in the region where a channel is formed are preferably reduced as much as possible. For example, oxygen is supplied to the oxide 230 through the insulator 250 or the like to fill the oxygen vacancies. Thus, a transistor that has stable electrical characteristics with a small variation in electrical characteristics and improved reliability can be provided.

As illustrated in FIG. 1(B), in the transistor 200, the oxide 243 (the oxide 243 a and the oxide 243 b) is provided between the oxide 230 b and the conductor 242 (the conductor 242 a and the conductor 242 b) which functions as the source electrode or the drain electrode. This structure in which the conductor 242 and the oxide 230 b are not in contact with each other can prevent the conductor 242 from absorbing oxygen in the oxide 230. That is, inhibiting oxidization of the conductor 242 can inhibit the decrease in conductivity of the conductor 242. Accordingly, the oxide 243 preferably has a function of inhibiting oxidization of the conductor 242.

The oxide 243 preferably has conductivity. When the oxide 243 which has conductivity is provided between the conductor 242, which functions as the source electrode or the drain electrode, and the oxide 230 b, the electrical resistance between the conductor 242 and the oxide 230 b is reduced, which is preferable. Such a structure improves the electrical characteristics and reliability of the transistor 200. The oxide 243 may have a crystalline structure.

For the oxide 243, an oxide containing zinc can be used. For example, zinc oxide, gallium zinc oxide, indium zinc oxide, or indium gallium zinc oxide can be used. Alternatively, indium oxide or indium tin oxide may be used. The oxide 243 is preferably a metal oxide having high bond energy between a metal atom and an oxygen atom. The conductivity of the oxide 243 is preferably higher than that of the oxide 230 (the oxide 230 a, the oxide 230 b, and the oxide 230 c). The thickness of the oxide 243 is preferably greater than or equal to 1 nm and less than or equal to 10 nm, further preferably greater than or equal to 1 nm and less than or equal to 5 nm. The oxide 243 preferably has crystallinity. The oxide 243 with crystallinity efficiently inhibits release of oxygen from the oxide 230. When the oxide 243 has a hexagonal crystal structure, for example, release of oxygen from the oxide 230 can sometimes be inhibited.

As shown in FIGS. 1(B) and 1(C), the transistor 200 of one embodiment of the present invention has a structure in which the insulator 282 and the insulator 250 are directly in contact with each other. With such a structure, oxygen contained in the insulator 280 is less likely to be absorbed into the conductor 260. Therefore, oxygen contained in the insulator 280 can be injected into the oxide 230 a and the oxide 230 b efficiently through the oxide 230 c; hence, oxygen vacancies in the oxide 230 a and the oxide 230 b can be reduced and the electrical characteristics and the reliability of the transistor 200 can be improved. In addition, the mixing of impurities such as hydrogen contained in the insulator 280 into the insulator 250 can be inhibited, which can inhibit the adverse effects on the electrical characteristics and the reliability of the transistor 200. For the insulator 282, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used.

The insulator 272 and the insulator 273 preferably have a function of inhibiting the transmission of oxygen and impurities such as hydrogen and water.

FIG. 3(A) is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 1(A), and is also a cross-sectional view in the channel width direction of one of a source region and a drain region of the transistor 200. As illustrated in FIG. 3(A), a structure is employed in which the top surface of the conductor 242 b, the side surface of the conductor 242 b, the side surface of the oxide 230 a, and the side surface of the oxide 230 b are covered with the insulator 272 and the insulator 273; thus, oxygen and impurities such as hydrogen and water can be inhibited from being diffused into the conductor 242 b from the side surface direction of the conductor 242 b and the top surface direction of the conductor 242 b. Furthermore, the bottom surface of the conductor 242 b is in contact with the oxide 243 b, and oxygen from the oxide 230 b is blocked by the oxide 243 b and thus prevented from being diffused into the conductor 242 b. Diffusion of oxygen from the periphery of the conductor 242 b into the conductor 242 b can be inhibited, so that the oxidation of the conductor 242 b can be inhibited. Note that a similar effect can also be obtained with the conductor 242 a. Impurities such as hydrogen and water can be inhibited from being diffused into the oxide 230 a and the oxide 230 b from the side surface direction of the oxide 230 a and the side surface direction of the oxide 230 b. For the insulator 272, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. For the insulator 273, aluminum oxide or hafnium oxide can be used, for example.

FIG. 3(B) is a cross-sectional view of a portion indicated by a dashed-dotted line A7-A8 in FIG. 1(A), which corresponds to a cross-sectional view in the channel width direction of the conductor 240 b electrically connected to the transistor 200 and functioning as a plug. Since the insulator 241 b is provided on a side surface of the conductor 240 b as illustrated in FIG. 3(B), oxygen and impurities such as hydrogen and water from the insulator 280 can be inhibited from being diffused into the conductor 240 b. Note that a similar effect can also be obtained with the conductor 240 a.

As illustrated in FIG. 1(C), when the bottom surface of the insulator 224 is used as a reference, the level of the bottom surface of the conductor 260 in a region where the oxide 230 a and the oxide 230 b do not overlap with the conductor 260 is preferably positioned lower than the level of a bottom surface of the oxide 230 b. The difference between the level of the bottom surface of the conductor 260 in a region where the oxide 230 b does not overlap with the conductor 260 and the level of the bottom surface of the oxide 230 b is set to greater than or equal to 0 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm, further preferably greater than or equal to 5 nm and less than or equal to 20 nm.

As described above, the conductor 260, which functions as the gate electrode, covers the side surface and the top surface of the oxide 230 b of the channel formation region, with the oxide 230 c and the insulator 250 positioned therebetween; this enables the electrical field of the conductor 260 to easily affect the entire oxide 230 b of the channel formation region. Consequently, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.

Accordingly, a semiconductor device that includes a transistor having a high on-state current can be provided. Alternatively, a semiconductor device that includes a transistor having excellent frequency characteristics can be provided. Alternatively, a semiconductor device that has stable electrical characteristics with a small variation in electrical characteristics and improved reliability can be provided. Alternatively, a semiconductor device that includes a transistor having a low off-state current can be provided.

The structure of the semiconductor device including the transistor 200 of one embodiment of the present invention is described in detail below.

The conductor 205 is placed to overlap with the oxide 230 and the conductor 260. Furthermore, the conductor 205 is preferably provided to be embedded in the insulator 214 and the insulator 216.

The conductor 260 sometimes functions as a first gate (also referred to as a top gate) electrode. The conductor 205 sometimes functions as a second gate (also referred to as a bottom gate) electrode. In that case, the V_(th) of the transistor 200 can be controlled by changing a potential applied to the conductor 205 independently of a potential applied to the conductor 260. In particular, the V_(th) of the transistor 200 can be higher than 0 V and the off-state current can be reduced by applying a negative potential to the conductor 205. Thus, a drain current when a potential applied to the conductor 260 is 0 V can be smaller in the case where a negative potential is applied to the conductor 205 than in the case where the negative potential is not applied to the conductor 205.

As illustrated in FIG. 1(A), the conductor 205 is preferably provided to be larger than a region of the oxide 230 that does not overlap with the conductor 242 a or the conductor 242 b. As illustrated in FIG. 1(C), it is particularly preferable that the conductor 205 extend to a region outside an end portion of the oxide 230 that intersects with the channel width direction. That is, the conductor 205 and the conductor 260 preferably overlap with each other with the insulators therebetween on an outer side of the side surface of the oxide 230 in the channel width direction. A large conductor 205 can sometimes reduce local charging, (referred to as charge up) in a treatment using plasma of a fabrication step after the formation of the conductor 205. Note that one embodiment of the present invention is not limited thereto. The conductor 205 is at least overlapped with the oxide 230 positioned between the conductor 242 a and the conductor 242 b.

With the above structure, the channel formation region can be electrically surrounded by the electric field of the conductor 260 having a function of the first gate electrode and the electric field of the conductor 205 having a function of the second gate electrode. In this specification, the transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

The conductor 205 a is preferably a conductor that inhibits the transmission of oxygen and impurities such as water and hydrogen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used for the conductor 205 a. Moreover, the conductor 205 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Although the conductor 205 is illustrated as having two layers, the conductor 205 can have a multilayer structure with three or more layers.

Here, it is preferable that as an oxide semiconductor, an insulator or a conductor positioned below the oxide semiconductor, and an insulator or a conductor positioned over the oxide semiconductor, different kinds of films are successively deposited without being exposed to the air, whereby a substantially highly purified intrinsic oxide semiconductor film whose impurity (hydrogen and water, in particular) concentration is reduced can be formed.

For example, insulating films to be the insulator 222, and the insulator 224 positioned over the insulator 216 and the conductor 205, an oxide film to be the oxide 230 a, an oxide film to be the oxide 230 b, an oxide film to be the oxide 243, and a conductive film to be the conductor 242 may be successively deposited in this order using a deposition apparatus including six treatment chambers.

The insulator 214 and the insulator 272, and the insulator 281 preferably function as a barrier insulating film that inhibits impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Thus, the insulator 214, the insulator 272, and the insulator 281 are preferably formed using an insulating material having a function of inhibiting diffusion of impurities (through which the impurities are unlikely to pass) such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N₂O, NO, or NO₂), or a copper atom. Alternatively, it is preferable to use an insulating material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (or through which the above oxygen is less likely to pass).

For example, it is preferable that silicon nitride or the like be used for the insulator 214, the insulator 272, and the insulator 281. Accordingly, impurities such as water or hydrogen can be inhibited from being diffused into the transistor 200 side from the substrate side through the insulator 214. Alternatively, oxygen contained in the insulator 224 and the like can be prevented from being diffused to the substrate side of the insulator 214. Impurities such as water or hydrogen can be inhibited from diffusing into the transistor 200 side from the insulator 280 and/or the conductor 246 and the like, which are provided above the insulator 272.

The resistivities of the insulator 214, the insulator 272, and the insulator 281 are preferably low in some cases. For example, by setting the resistivities of the insulator 214, the insulator 272, and the insulator 281 to approximately 1×10¹³ Ωcm, the insulator 214, the insulator 272, and the insulator 281 can reduce charge up of the conductor 205, the conductor 242 or the conductor 260 in a treatment using plasma or the like of a fabrication step of a semiconductor device in some cases. The resistivities of the insulator 214, the insulator 272, and the insulator 281 are preferably higher than or equal to 1×10¹⁰ Ωcm and lower than or equal to 1×10¹⁵ Ωcm.

The insulator 214 may have a stacked-layer structure. For example, it is suitable to use a stacked-layer structure of an aluminum oxide film and a silicon nitride film for the insulator 214. With the aluminum oxide film, oxygen can be supplied to a lower part of the insulator 214. Furthermore, diffusion of impurities such as hydrogen and water that enter the transistor 200 side from the substrate side can be inhibited by the silicon nitride film.

The insulator 216, the insulator 280, and the insulator 274 preferably have a lower dielectric constant than the insulator 214. When a material having a low dielectric constant is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 216, the insulator 280, and the insulator 274, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is used, for example.

The insulator 222 and the insulator 224 have a function of a gate insulator.

Here, it is preferable that oxygen be released from the insulator 224 in contact with the oxide 230 by heating. In this specification, oxygen that is released by heating is referred to as excess oxygen in some cases. For example, silicon oxide, silicon oxynitride, or the like is used for the insulator 224 as appropriate. When an insulator containing oxygen is provided in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

As the insulator 224, specifically, an oxide material from which part of oxygen is released by heating is preferably used. An oxide that releases oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen molecules is greater than or equal to 1.0×10¹⁸ molecules/cm³, preferably greater than or equal to 1.0×10¹⁹ molecules/cm³, further preferably greater than or equal to 2.0×10¹⁹ molecules/cm³ or greater than or equal to 3.0×10²⁰ molecules/cm³ in TDS (Thermal Desorption Spectroscopy) analysis. Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 400° C.

The insulator 222 preferably functions as a barrier insulating film that inhibits an impurity such as water or hydrogen from being mixed in the transistor 200 from the substrate side. For example, the insulator 222 has the property of being less likely to transmit hydrogen than the insulator 224. Surrounding the insulator 224, the oxide 230, and the like by the insulator 222 and the insulator 272 can inhibit entry of an impurity such as water or hydrogen into the transistor 200 from the outside.

Furthermore, the insulator 222 preferably has a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (or is preferably less likely to transmit the above oxygen). For example, the insulator 222 preferably has the property of being less likely to transmit oxygen than the insulator 224. The insulator 222 preferably has a function of inhibiting diffusion of oxygen or impurities, in which case diffusion of oxygen included in the oxide 230 into a layer under the insulator 222 can be reduced. Furthermore, the conductor 205 can be inhibited from reacting with oxygen included in the insulator 224 or the oxide 230.

Furthermore, it is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material, for the insulator 222. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that inhibits release of oxygen from the oxide 230 and mixing of impurities such as hydrogen from the periphery of the transistor 200 in the oxide 230.

Alternatively, to these insulators, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added, for example. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

For example, a single layer or a stacked layer of an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO₃), or (Ba,Sr)TiO₃ (BST) may be used for the insulator 222. With miniaturization and high integration of a transistor, a problem such as leakage current may arise because of a thinner gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a gate potential during operation of the transistor can be reduced while the physical thickness of the gate insulator is kept.

Note that the insulator 222 and the insulator 224 may each have a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed.

The oxide 230 includes the oxide 230 a, the oxide 230 b over the oxide 230 a, and the oxide 230 c over the oxide 230 b. When the oxide 230 a is provided below the oxide 230 b, impurities can be inhibited from diffusing into the oxide 230 b from the components formed below the oxide 230 a. When the oxide 230 c is provided over the oxide 230 b, impurities can be inhibited from diffusing into the oxide 230 b from the components formed above the oxide 230 c.

Note that the oxide 230 preferably has a stacked-layer structure using oxides which differ in the atomic ratio of metal atoms. Specifically, the atomic proportion of the element M in constituent elements in the metal oxide used as the oxide 230 a is preferably greater than the atomic proportion of the element M in constituent elements in the metal oxide used as the oxide 230 b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxide 230 a is preferably greater than the atomic ratio of the element M to In in the metal oxide used as the oxide 230 b. Furthermore, the atomic ratio of In to the element M in the metal oxide used as the oxide 230 b is preferably greater than the atomic ratio of In to the element M in the metal oxide used as the oxide 230 a. A metal oxide that can be used as the oxide 230 a or the oxide 230 b can be used as the oxide 230 c.

The oxide 230 b preferably has crystallinity. For example, a CAAC-OS (c-axis aligned crystalline oxide semiconductor) described later is preferably used. An oxide having crystallinity, such as a CAAC-OS, has a dense structure with small amounts of impurities and defects (oxygen vacancies or the like) and high crystallinity. This can inhibit oxygen extraction from the oxide 230 b by the source electrode or the drain electrode. This can reduce oxygen extraction from the oxide 230 b even when heat treatment is performed; hence, the transistor 200 is stable with respect to high temperatures in the manufacturing process (what is called thermal budget).

The energy of the conduction band minimum of each of the oxide 230 a and the oxide 230 c is preferably higher than the energy of the conduction band minimum of the oxide 230 b. In other words, the electron affinity of each of the oxide 230 a and the oxide 230 c is preferably smaller than the electron affinity of the oxide 230 b.

Here, the energy level of the conduction band minimum is gradually varied at a junction region of the oxide 230 a, the oxide 230 b, and the oxide 230 c. In other words, the energy level of the conduction band minimum at a junction region of each of the oxide 230 a, the oxide 230 b, and the oxide 230 c is continuously varied or continuously connected. To obtain this, the densities of defect states in mixed layers formed at an interface between the oxide 230 a and the oxide 230 b and an interface between the oxide 230 b and the oxide 230 c are preferably made low.

Specifically, as the oxide 230 a, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] is used. As the oxide 230 b, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] or 1:1:1 [atomic ratio] is used. As the oxide 230 c, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or Ga:Zn=2:5 [atomic ratio] is used. Specific examples of the oxide 230 c having a stacked-layer structure include a stacked-layer structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a stacked-layer structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a stacked-layer structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a stacked-layer structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

At this time, the oxide 230 b serves as a main carrier path. When the oxide 230 a and the oxide 230 c have the above structure, the density of defect states at the interface between the oxide 230 a and the oxide 230 b and the interface between the oxide 230 b and the oxide 230 c can be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor 200 can have a high on-state current and excellent frequency characteristics. Note that in the case where the oxide 230 c has a stacked-layer structure, not only the above effect of reducing the density of defect states at the interface between the oxide 230 b and the oxide 230 c but also the effect of inhibiting diffusion of a constituent element included in the oxide 230 c to the insulator 250 side should be obtained. More specifically, the oxide 230 c has a stacked-layer structure and an oxide not including In is positioned in the upper portion of the stacked layer structure, so that In, which can diffuse to the insulator 250 side, can be inhibited. Since the insulator 250 functions as the gate insulator, the transistor has defects in characteristics when In diffuses. Thus, when the oxide 230 c has a stacked-layer structure, a highly reliable semiconductor device can be provided.

As the oxide 230, a metal oxide functioning as an oxide semiconductor is preferably used. For example, a metal oxide whose energy gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, is preferably used. With the use of a metal oxide having such a large energy gap, the off-state current of the transistor can be reduced. With use of such a transistor, a semiconductor device with low power consumption can be provided.

Electron affinity or conduction band minimum Ec can be obtained from an energy gap Eg and an ionization potential Ip, which is a difference between a vacuum level and an energy of valence band maximum Ev, as shown in FIG. 12. The ionization potential I_(p) can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) apparatus. The energy gap E_(g) can be measured using, for example, a spectroscopic ellipsometer.

The oxide 243 is provided over the oxide 230 b, and the conductor 242 (the conductor 242 a and the conductor 242 b) functioning as the source electrode and the drain electrode is provided over the oxide 243. The thickness of the conductor 242 is, for example, greater than or equal to 1 nm and less than or equal to 50 nm, preferably greater than or equal to 2 nm and less than or equal to 25 nm.

For the conductor 242, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that retain their conductivity even after absorbing oxygen.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably placed in contact with the inner side (the top surface and the side surface) of the oxide 230 c. For the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride, which are thermally stable, are preferable.

The insulator 250 is preferably formed using an insulator from which oxygen is released by heating as in the insulator 224. When an insulator from which oxygen is released by heating is provided as the insulator 250 in contact with the top surface of the oxide 230 c, oxygen can be efficiently supplied to the channel formation region of the oxide 230 b. Furthermore, as in the insulator 224, the concentration of an impurity such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably inhibits diffusion of oxygen from the insulator 250 to the conductor 260. Provision of the metal oxide that inhibits diffusion of oxygen inhibits diffusion of oxygen from the insulator 250 to the conductor 260. That is, a reduction in the amount of excess oxygen supplied to the oxide 230 can be inhibited. In addition, oxidation of the conductor 260 due to oxygen from the insulator 250 can be inhibited.

The metal oxide has a function of part of the gate insulator in some cases. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, a metal oxide that is a high-k material with a high relative permittivity is preferably used as the metal oxide. When the gate insulator has a stacked-layer structure of the insulator 250 and the metal oxide, the stacked-layer structure can be thermally stable and have a high relative permittivity. Accordingly, a gate potential that is applied during operation of the transistor can be reduced while the physical thickness of the gate insulator is kept. In addition, the equivalent oxide thickness (EOT) of an insulator functioning as the gate insulator can be reduced.

Specifically, a metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. It is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

The metal oxide has a function of part of the gate electrode in some cases. In that case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

It is particularly preferable to use, for the conductor functioning as the gate electrode, a conductive material containing oxygen and a metal element contained in a metal oxide where the channel is formed. Alternatively, a conductive material containing the above metal element and nitrogen may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. With use of such a material, hydrogen contained in the metal oxide where the channel is formed can be trapped in some cases. Alternatively, hydrogen entering from an external insulator or the like can be trapped in some cases.

Although the conductor 260 has a two-layer structure in FIG. 1, a single-layer structure or a stacked-layer structure of three or more layers may be employed.

For the conductor 260 a, it is preferable to use a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N₂O, NO, NO₂, or the like), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

When the conductor 260 a has a function of inhibiting diffusion of oxygen, the conductivity of the conductor 260 b can be inhibited from being lowered because of oxidation due to oxygen included in the insulator 250. As a conductive material having a function of inhibiting diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

Moreover, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 260 b. As the conductor 260 also functioning as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. In addition, the conductor 260 b may have a stacked-layer structure, for example, a stacked-layer structure of any of the above conductive materials and titanium or titanium nitride.

For example, as the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is preferably included. In particular, silicon oxide and silicon oxynitride, which are thermally stable, are preferable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide, in each of which a region containing oxygen that is released by heating can be easily formed, are particularly preferable.

The concentration of an impurity such as water or hydrogen included in the insulator 280 is preferably lowered. A top surface of the insulator 280 may be planarized.

The insulator 282 preferably functions as a barrier insulating film that inhibits impurities such as water and hydrogen from entering the insulator 280 from the above. As the insulator 282, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used.

The insulator 274 functioning as an interlayer film is preferably provided over the insulator 282. As in the insulator 224 or the like, the concentration of impurities such as water or hydrogen in the insulator 274 is preferably lowered.

For the conductor 240 a and the conductor 240 b, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. In addition, the conductor 240 a and the conductor 240 b may have a stacked-layer structure.

In the case where the conductor 240 has a stacked-layer structure, a conductive material having a function of inhibiting the transmission of an impurity such as water or hydrogen is preferably used for a conductor in contact with the insulator 281, the insulator 274, the insulator 282, the insulator 280, the insulator 273, and the insulator 272. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. A single layer or a stacked layer of the conductive material having a function of inhibiting the transmission of impurities such as water or hydrogen may be used. The use of the conductive material can prevent oxygen added to the insulator 280 from being absorbed by the conductor 240 a and the conductor 240 b. Moreover, the mixing of impurities such as water or hydrogen into the oxide 230 through the conductor 240 a and the conductor 240 b from a layer above the insulator 281 can be inhibited.

As the insulator 241 a and the insulator 241 b, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used. Since the insulator 241 a and the insulator 241 b are provided in contact with the insulator 272 and the insulator 273, the mixing of impurities such as water or hydrogen into the oxide 230 through the conductor 240 a and the conductor 240 b from the insulator 280 or the like can be inhibited. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240 a and the conductor 240 b.

The conductor 246 (the conductor 246 a and the conductor 246 b) functioning as a wiring may be provided in contact with a top surface of the conductor 240 a and a top surface of the conductor 240 b. The conductor 246 is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Furthermore, the conductor may have a stacked-layer structure; for example, stacked layers of the above conductive material, and titanium or titanium nitride. Note that the conductor may be formed to be embedded in an opening provided in an insulator.

<Constituent Material of Semiconductor Device>

Constituent materials that can be used for the semiconductor device will be described below.

<Substrate>

As a substrate over which the transistor 200 is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (an yttria-stabilized zirconia substrate or the like), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate of silicon, germanium, or the like and a compound semiconductor substrate including silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Moreover, a semiconductor substrate in which an insulator region is included in the above semiconductor substrate, e.g., an SOI (Silicon On Insulator) substrate or the like is used. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. A substrate including a metal nitride, a substrate including a metal oxide, or the like is used. Moreover, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like is used. Alternatively, any of these substrates provided with an element may be used. Examples of the element provided for the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

<Insulator>

Examples of an insulator include an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide, each of which has an insulating property.

With miniaturization and high integration of a transistor, a problem such as leakage current may arise because of a thinner gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a voltage during operation of the transistor can be reduced while the physical thickness of the gate insulator is kept. By contrast, when a material with a low relative permittivity is used for the insulator functioning as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Accordingly, a material is preferably selected depending on the function of an insulator.

Examples of the insulator having a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

Examples of the insulator with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

When a transistor using an oxide semiconductor is surrounded by insulators having a function of inhibiting transmission of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stable. As the insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen, a single layer or a stacked layer of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Specifically, as the insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide or silicon nitride; or the like can be used.

In addition, the insulator functioning as the gate insulator is preferably an insulator including a region containing oxygen that is released by heating. When a structure is employed in which silicon oxide or silicon oxynitride including a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies included in the oxide 230 can be compensated for.

<Conductor>

For the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that retain their conductivity even after absorbing oxygen. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

Furthermore, a stack including a plurality of conductive layers formed with the above materials may be used. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. Furthermore, a stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. Furthermore, a stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

Note that when an oxide is used for the channel formation region of the transistor, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen is preferably employed for the conductor functioning as the gate electrode. In that case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

It is particularly preferable to use, for the conductor functioning as the gate electrode, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed. Furthermore, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. With the use of such a material, hydrogen included in the metal oxide in which a channel is formed can be trapped in some cases. Alternatively, hydrogen mixed from an external insulator or the like can be trapped in some cases.

<Metal Oxide>

As the oxide 230, a metal oxide functioning as an oxide semiconductor is preferably used. A metal oxide that can be used as the oxide 230 of the present invention will be described below

The metal oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. Furthermore, aluminum, gallium, yttrium, tin, or the like is preferably contained in addition to them. Furthermore, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.

Here, the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc is considered. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Examples of other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that a plurality of the above-described elements may be combined as the element M.

Note that in this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide in some cases. Alternatively, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Structure of Metal Oxide]

Oxide semiconductors (metal oxides) can be classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductors include a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

The CAAC-OS has c-axis alignment, a plurality of nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that the distortion refers to a portion where the direction of a lattice arrangement changes between a region with a regular lattice arrangement and another region with a regular lattice arrangement in a region where the plurality of nanocrystals are connected.

The nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in some cases. Furthermore, a pentagonal or heptagonal lattice arrangement, for example, is included in the distortion in some cases. Note that a clear crystal grain boundary (also referred to as grain boundary) is difficult to observe even in the vicinity of distortion in the CAAC-OS. That is, formation of a crystal grain boundary is inhibited by the distortion of a lattice arrangement. This is because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in the a-b plane direction, an interatomic bond length changed by substitution of a metal element, and the like.

Furthermore, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element M in the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. Furthermore, when indium in the In layer is replaced with the element M, the layer can be referred to as an (In,M) layer.

The CAAC-OS is a metal oxide with high crystallinity. By contrast, in the CAAC-OS, a reduction in electron mobility due to the crystal grain boundary is less likely to occur because it is difficult to observe a clear crystal grain boundary. Furthermore, mixing of impurities, formation of defects, or the like might decrease the crystallinity of a metal oxide, which means that the CAAC-OS is a metal oxide having small amounts of impurities and defects (e.g., oxygen vacancies (VO)). Thus, a metal oxide including a CAAC-OS is physically stable. Therefore, the metal oxide including a CAAC-OS is resistant to heat and has high reliability.

In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. Furthermore, there is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation in the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

Note that indium-gallium-zinc oxide (hereinafter referred to as IGZO) that is a kind of metal oxide containing indium, gallium, and zinc has a stable structure in some cases by being formed of the above-described nanocrystals. In some cases, IGZO has a stable structure when formed of smaller crystals (e.g., the above-described nanocrystals) rather than larger crystals (here, crystals with a size of several millimeters or several centimeters) because crystal growth tends to hardly occur particularly in the air.

An a-like OS is a metal oxide having a structure between those of the nc-OS and an amorphous oxide semiconductor. The a-like OS contains a void or a low-density region. That is, the a-like OS has low crystallinity as compared with the nc-OS and the CAAC-OS.

The oxide semiconductor (metal oxide) can have various structures which show different properties. Two or more kinds of the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS may be included in the oxide semiconductor of one embodiment of the present invention.

Note that a structure of an oxide semiconductor (metal oxide) in the semiconductor device of one embodiment of the present invention is not particularly limited; however, the oxide semiconductor preferably has crystallinity. For example, the oxide 230 can have a CAAC-OS structure and the oxide 243 can have a hexagonal crystal structure. The semiconductor device can have high reliability when the oxide 230 and the oxide 243 have the above crystal structures.

[Impurities]

Here, the influence of each impurity in the metal oxide will be described.

When the metal oxide contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor using a metal oxide that contains an alkali metal or an alkaline earth metal in its channel formation region is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of an alkali metal or an alkaline earth metal in the metal oxide. Specifically, the concentration of an alkali metal or an alkaline earth metal in the metal oxide obtained by SIMS (the concentration obtained by secondary ion mass spectrometry (SIMS)) is set lower than or equal to 1×10¹⁸ atoms/cm³, preferably lower than or equal to 2×10¹⁶ atoms/cm³.

Hydrogen included in a metal oxide reacts with oxygen bonded to a metal atom to become water, and thus forms an oxygen vacancy, in some cases. When hydrogen enters the oxygen vacancy, an electron which is a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron which is a carrier. Thus, a transistor using a metal oxide containing hydrogen is likely to have normally-on characteristics.

Accordingly, hydrogen in the metal oxide is preferably reduced as much as possible. Specifically, the hydrogen concentration of the metal oxide, which is obtained by SIMS, is set lower than 1×10²⁰ atoms/cm³, preferably lower than 1×10¹⁹ atoms/cm³, further preferably lower than 5×10¹⁸ atoms/cm³, still further preferably lower than 1×10¹⁸ atoms/cm³. When a metal oxide in which impurities are sufficiently reduced is used in a channel formation region of a transistor, stable electrical characteristics can be given.

Note that as a metal oxide used for a semiconductor of a transistor, a thin film having high crystallinity is preferably used. With the use of the thin film, the stability or the reliability of the transistor can be improved. Examples of the thin film include a thin film of a single-crystal metal oxide and a thin film of a polycrystalline metal oxide. However, to form the thin film of a single-crystal metal oxide or the thin film of a polycrystalline metal oxide over a substrate, a high-temperature process or a laser heating process is needed. Thus, the manufacturing process cost is increased, and in addition, the throughput is decreased.

Non-Patent Document 1 and Non-Patent Document 2 have reported that an In—Ga—Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was found in 2009. It has been reported that CAAC-IGZO has c-axis alignment, a crystal grain boundary is not clearly observed in CAAC-IGZO, and CAAC-IGZO can be formed over a substrate at low temperatures. It has also been reported that a transistor using CAAC-IGZO has excellent electrical characteristics and high reliability.

In addition, in 2013, an In—Ga—Zn oxide having an nc structure (referred to as nc-IGZO) was found (see Non-Patent Document 3). It has been reported that nc-IGZO has periodic atomic arrangement in a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) and there is no regularity of crystal orientation between different regions.

Non-Patent Document 4 and Non-Patent Document 5 have shown a change in average crystal size due to electron beam irradiation to thin films of the above CAAC-IGZO, the above nc-IGZO, and IGZO having low crystallinity. In the thin film of IGZO having low crystallinity, crystalline IGZO of approximately 1 nm was observed even before the electron beam irradiation. Thus, it has been reported that the existence of a completely amorphous structure was not observed in IGZO. In addition, it has been shown that the thin film of CAAC-IGZO and the thin film of nc-IGZO each have higher stability to electron beam irradiation than the thin film of IGZO having low crystallinity. Thus, the thin film of CAAC-IGZO or the thin film of nc-IGZO is preferably used for a semiconductor of a transistor.

Non-Patent Document 6 shows that a transistor using a metal oxide has an extremely low leakage current in an off state; specifically, the off-state current per micrometer in the channel width of the transistor is of the order of yA/μm (10⁻²⁴ A/μm). For example, a low-power-consumption CPU applying a characteristic of low leakage current of the transistor using a metal oxide is disclosed (see Non-Patent Document 7).

Furthermore, application of a transistor using a metal oxide to a display device that utilizes the characteristic of a low leakage current of the transistor has been reported (see Non-Patent Document 8). In the display device, a displayed image is changed several tens of times per second. The number of times an image is changed per second is referred to as a refresh rate. The refresh rate is also referred to as driving frequency. Such high-speed screen change that is hard for human eyes to recognize is considered as a cause of eyestrain. Thus, it is proposed that the refresh rate of the display device is lowered to reduce the number of times of image rewriting. Moreover, driving with a lowered refresh rate enables the power consumption of the display device to be reduced. Such a driving method is referred to as idling stop (IDS) driving.

The discovery of the CAAC structure and the nc structure has contributed to an improvement in electrical characteristics and reliability of a transistor using a metal oxide having the CAAC structure or the nc structure, a reduction in manufacturing cost, and an improvement in throughput. Furthermore, applications of the transistor to a display device and an LSI utilizing the characteristics of a low leakage current of the transistor have been studied.

<Method of Fabricating Semiconductor Device>

Next, a method of fabricating a semiconductor device including the transistor 200 according to the present invention, which is illustrated in FIG. 1, will be described with reference to FIG. 4 to FIG. 11. In FIG. 4 to FIG. 11, (A) of each drawing is a top view. Moreover, (B) of each drawing is a cross-sectional view corresponding to a portion indicated by the dashed-dotted line A1-A2 in (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Furthermore, (C) of each drawing is a cross-sectional view corresponding to a portion indicated by the dashed-dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. Note that for simplification of the drawings, some components are not illustrated in the top view of (A) of each drawing.

First, a substrate (not illustrated) is prepared, and the insulator 214 is deposited over the substrate. The insulator 214 can be deposited by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

Note that CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD methods can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas to be used.

By a plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Furthermore, a thermal CVD method is a deposition method that does not use plasma and thus enables less plasma damage to an object. For example, a wiring, an electrode, an element (e.g., transistor or capacitor), or the like included in a semiconductor device might be charged up by receiving charges from plasma. In this case, accumulated charges might break the wiring, electrode, element, or the like included in the semiconductor device. By contrast, in the case of a thermal CVD method that does not use plasma, such plasma damage is not caused and the yield of the semiconductor device can be increased. Furthermore, a thermal CVD method does not cause plasma damage during deposition, so that a film with few defects can be obtained.

In an ALD method, one atomic layer can be deposited at a time using self-regulating characteristics of atoms. Hence, an ALD method has effects such as deposition of an extremely thin film, deposition on a component with a large aspect ratio, deposition of a film with a small number of defects such as pinholes, deposition with excellent coverage, and low-temperature deposition. An ALD method includes a PEALD (plasma-enhanced ALD) method, which is a deposition method using plasma. The use of plasma is sometimes preferable because deposition at a lower temperature is possible. Note that a precursor used in an ALD method sometimes contains impurities such as carbon. Thus, in some cases, a film provided by an ALD method contains impurities such as carbon in a larger amount than a film provided by another deposition method. Note that impurities can be quantified by X-ray photoelectron spectroscopy (XPS).

Unlike a deposition method in which particles ejected from a target or the like are deposited, a CVD method and an ALD method are deposition methods in which a film is formed by reaction at a surface of an object. Thus, a CVD method and an ALD method are deposition methods that enable favorable step coverage almost regardless of the shape of an object. In particular, an ALD method enables excellent step coverage and excellent thickness uniformity and thus is suitable for covering a surface of an opening portion with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate; thus, it is sometimes preferable to combine an ALD method with another deposition method with a high deposition rate such as a CVD method.

A CVD method and an ALD method enable control of the composition of a film to be obtained with a flow rate ratio of the source gases. For example, by a CVD method or an ALD method, a film with a certain composition can be deposited depending on a flow rate ratio of the source gases. Moreover, by a CVD method or an ALD method, by changing the flow rate ratio of the source gases during the deposition, a film whose composition is continuously changed can be deposited. In the case of depositing while changing the flow rate ratio of the source gases, as compared with the case of depositing with the use of a plurality of deposition chambers, time taken for the deposition can be shortened because time taken for transfer and pressure adjustment is omitted. Thus, productivity of semiconductor devices can be improved in some cases.

In this embodiment, for the insulator 214, silicon nitride is deposited by a CVD method. As described here, an insulator through which copper is less likely to pass, such as silicon nitride, is used for the insulator 214; accordingly, even when a metal that is likely to diffuse, such as copper, is used for a conductor in a layer (not illustrated) below the insulator 214, diffusion of the metal to a layer above the insulator 214 can be inhibited.

Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Then, an opening reaching the insulator 214 is formed in the insulator 216. Note that examples of the opening include a groove and a slit. A region where the opening is formed may be referred to as an opening portion. Wet etching can be used for the formation of the openings; however, dry etching is preferably used for microfabrication. As the insulator 214, it is preferable to select an insulator that functions as an etching stopper film used in forming the groove by etching the insulator 216. For example, in the case where a silicon oxide film is used as the insulator 216 in which the groove is to be formed, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the insulator 214.

After the formation of the opening, a conductive film to be the conductor 205 is deposited. The conductive film preferably includes a conductor that has a function of inhibiting the transmission of oxygen. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a stacked-layer film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film to be the conductor 205 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, the conductive film to be the conductor 205 has a multilayer structure. First, tantalum nitride is deposited by a sputtering method, and titanium nitride is stacked over the tantalum nitride. Even when a metal that is likely to diffuse, such as copper, is used for an upper layer of the conductive film to be the conductor 205 described below, the use of such metal nitrides for a lower layer of the conductive film to be the conductor 205 can prevent outward diffusion of the metal from the conductor 205.

Next, a conductive film that is the upper layer of the conductive film to be the conductor 205 is deposited. The conductive film can be deposited by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the conductive film of the upper layer of the conductive film to be the conductor 205, a low-resistance conductive material such as copper is deposited.

Next, CMP treatment is performed to remove parts of the upper layer of the conductive film to be the conductor 205 and the lower layer of the conductive film to be the conductor 205, so that the insulator 216 is exposed. As a result, the conductive film to be the conductor 205 remains only in the opening portion. Thus, the conductor 205 whose top surface is flat can be formed. Note that the insulator 216 is partly removed by the CMP treatment in some cases (see FIG. 4).

Here, a method of forming the conductor 205 which is different from the above will be described below.

Next, the conductive film to be the conductor 205 is deposited over the insulator 214. The conductive film to be the conductor 205 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In addition, the conductive film to be the conductor 205 can be a multilayer film. In this embodiment, tungsten is deposited for the conductive film to be the conductor 205.

Next, the conductive film to be the conductor 205 is processed by a lithography method, so that the conductor 205 is formed.

In the lithography method, first, a resist is exposed to light through a mask. Next, a region exposed to light is removed or left using a developing solution, so that a resist mask is formed. Then, etching treatment through the resist mask is conducted, whereby a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. The resist mask is formed by, for example, exposure of the resist to light using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be employed in which a portion between a substrate and a projection lens is filled with liquid (e.g., water) to perform light exposure. An electron beam or an ion beam may be used instead of the above-mentioned light. Note that a mask is not necessary in the case of using an electron beam or an ion beam. Note that the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment.

A hard mask formed of an insulator or a conductor may be used instead of the resist mask. In the case where a hard mask is used, a hard mask with a desired shape can be formed by forming an insulating film or a conductive film that is the hard mask material over the conductive film to be the conductor 205, forming a resist mask thereover, and then etching the hard mask material. The etching of the conductive film to be the conductor 205 may be performed after removal of the resist mask or with the resist mask remaining. In the latter case, the resist mask sometimes disappears during the etching. The hard mask may be removed by etching after the etching of the conductive film to be the conductor 205. The hard mask does not need to be removed in the case where the material of the hard mask does not affect the following process or can be utilized in the following process.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate type electrodes can be used. The capacitively coupled plasma etching apparatus including the parallel plate type electrodes may have a structure in which a high-frequency power is applied to one of the parallel plate type electrodes. Alternatively, a structure may be employed in which different high-frequency powers are applied to one of the parallel plate type electrodes. Alternatively, a structure may be employed in which high-frequency power sources with the same frequency are applied to the parallel plate type electrodes. Alternatively, a structure may be employed in which high-frequency power sources with different frequencies are applied to the parallel plate type electrodes. Alternatively, a dry etching apparatus including a high-density plasma source can be used. As the dry etching apparatus including a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used, for example.

Next, an insulating film to be the insulator 216 is deposited over the insulator 214 and the conductor 205. The insulating film to be insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulating film to be insulator 216, silicon oxide is deposited by a CVD method.

Here, the thickness of the insulating film to be the insulator 216 is preferably greater than or equal to the thickness of the conductor 205. For example, when the thickness of the conductor 205 is 1, the thickness of the insulating film to be the insulator 216 is greater than or equal to 1 and less than or equal to 3. In this embodiment, the thickness of the conductor 205 is 150 nm and the thickness of the insulating film to be the insulator 216 is 350 nm.

Next, CMP (chemical Mechanical Polishing) treatment is performed on the insulating film to be the insulator 216, so that part of the insulating film to be the insulator 216 is removed and a surface of the conductor 205 is exposed. Thus, the conductor 205 and the insulator 216 whose top surfaces are flat can be formed. The above is another method of forming the conductor 205. FIG. 2 illustrates an example of a semiconductor device including the transistor 200 in which the conductor 205 and the insulator 216 are formed in the above manner.

Next, the insulator 222 is deposited over the insulator 216 and the conductor 205. An insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited as the insulator 222. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in structure bodies provided around the transistor 200 are inhibited from diffusing into the transistor 200 through the insulator 222, and generation of oxygen vacancies in the oxide 230 can be inhibited.

The insulator 222 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Then, an insulating film 224A is deposited over the insulator 222. The insulating film 224A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Sequentially, heat treatment is preferably performed. The heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., further preferably higher than or equal to 320° C. and lower than or equal to 450° C. Note that the heat treatment is performed in a nitrogen atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Alternatively, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in a nitrogen atmosphere or an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen.

In this embodiment, treatment is performed at 400° C. in a nitrogen atmosphere for an hour, and successively another treatment is performed at 400° C. in an oxygen atmosphere for an hour. By the heat treatment, impurities such as water and hydrogen included in the insulating film 224A can be removed.

The above heat treatment may be performed after the insulator 222 is deposited. For the heat treatment, the conditions for the above-described heat treatment can be used.

Here, plasma treatment containing oxygen may be performed under reduced pressure so that an excess-oxygen region can be formed in the insulating film 224A. The plasma treatment containing oxygen is preferably performed using an apparatus including a power source for generating high-density plasma using microwaves, for example. Alternatively, a power source for applying an RF (Radio Frequency) to a substrate side may be included. The use of high-density plasma enables high-density oxygen radicals to be produced, and RF application to the substrate side allows the oxygen radicals generated by the high-density plasma to be efficiently introduced into the insulating film 224A. Alternatively, after plasma treatment containing an inert gas is performed with this apparatus, plasma treatment containing oxygen may be performed to compensate for released oxygen. Note that impurities such as water and hydrogen included in the insulating film 224A can be removed by selecting the conditions for the plasma treatment appropriately. In that case, the heat treatment is not necessarily performed.

Here, aluminum oxide may be deposited over the insulating film 224A by a sputtering method and the aluminum oxide may be subjected to CMP until the insulating film 224A is reached. The CMP treatment can planarize the surface of the insulating film 224A and smooth the surface of the insulating film 224A. When the CMP treatment is performed on the aluminum oxide placed over the insulating film 224A, it is easy to detect the endpoint of CMP. Although part of the insulating film 224A is polished by CMP and the thickness of the insulating film 224A is reduced in some cases, the thickness can be adjusted when the insulating film 224A is deposited. Planarizing and smoothing the surface of the insulating film 224A can improve the coverage with an oxide deposited later and a decrease in the yield of the semiconductor device in some cases. The deposition of aluminum oxide over the insulating film 224A by a sputtering method is preferred because oxygen can be added to the insulating film 224A.

Next, an oxide film 230A to be the oxide 230 a and an oxide film 230B to be the oxide 230 b are deposited in this order over the insulating film 224A (see FIG. 4). Note that the oxide films are preferably deposited successively without exposure to an air atmosphere. By the deposition without exposure to the air, impurities or moisture from the air atmosphere can be prevented from being attached to the top surfaces of the oxide film 230A and the oxide film 230B, so that the vicinity of an interface between the oxide film 230A and the oxide film 230B can be kept clean.

The oxide film 230A and the oxide film 230B can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the case where the oxide film 230A and the oxide film 230B are deposited by a sputtering method, for example, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. The amount of excess oxygen in the oxide film to be deposited can be increased by an increase in the proportion of oxygen included in the sputtering gas. In the case where the above oxide films are deposited by a sputtering method, the above In-M-Zn oxide target can be used.

In particular, when the oxide film 230A is deposited, part of oxygen included in the sputtering gas is supplied to the insulating film 224A in some cases. Therefore, the proportion of oxygen included in the sputtering gas for the oxide film 230A is preferably 70% or higher, further preferably 80% or higher, and still further preferably 100%.

In the case where the oxide film 230B is formed by a sputtering method, when the proportion of oxygen included in the sputtering gas is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20% during the deposition, an oxygen-deficient oxide semiconductor is formed. In a transistor using an oxygen-deficient oxide semiconductor for its channel formation region, relatively high field-effect mobility can be obtained.

In this embodiment, the oxide film 230A is deposited by a sputtering method using a target with In:Ga:Zn=1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]) or a target with In:Ga:Zn=1:3:4 [atomic ratio]. The oxide film 230B is deposited by a sputtering method using a target with In:Ga:Zn=4:2:4.1 [atomic ratio] or 1:1:1 [atomic ratio]. Note that each of the oxide films is preferably formed to have characteristics required for the oxide 230 by appropriate selection of deposition conditions and an atomic ratio.

Next, heat treatment may be performed. For the heat treatment, the conditions for the above-described heat treatment can be used. Through the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed, for example. In this embodiment, treatment is performed at 400° C. in a nitrogen atmosphere for an hour, and successively another treatment is performed at 400° C. in an oxygen atmosphere for an hour.

Next, an oxide film 243A is deposited over the oxide film 230B. The oxide film 243A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, a conductive film 242A is deposited over the oxide film 243A. The conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 4).

Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into island shapes to form the oxide 230 a, the oxide 230 b, the oxide layer 243B, and a conductor layer 242B (see FIG. 5). Although not shown, in the step, the thickness of a region of the insulating film 224A which does not overlap with the oxide 230 a becomes small in some cases.

Here, the oxide 230 a, the oxide 230 b, the oxide layer 243B, and the conductor layer 242B are formed to at least partly overlap with the conductor 205. It is preferable that the side surfaces of the oxide 230 a, the oxide 230 b, the oxide layer 243B, and the conductor layer 242B be substantially perpendicular to a top surface of the insulator 222. When the side surfaces of the oxide 230 a, the oxide 230 b, the oxide layer 243B, and the conductor layer 242B are substantially perpendicular to the top surface of the insulator 222, the plurality of transistors 200 can be provided in a smaller area and at a higher density. Alternatively, a structure may be employed in which an angle formed by the side surfaces of the oxide 230 a, the oxide 230 b, the oxide layer 243B, and the conductor layer 242B and the top surface of the insulator 222 is a small angle. In that case, the angle formed by the side surfaces of the oxide 230 a, the oxide 230 b, the oxide layer 243B, and the conductor layer 242B and the top surface of the insulator 222 is preferably greater than or equal to 60° and less than 70°. With such a shape, the coverage with the insulator 272 and the like can be improved in a later step, so that defects such as a void can be reduced.

There is a curved surface between the side surface of the conductor layer 242B and the top surface of the conductor layer 242B. That is, an end portion of the side surface and an end portion of the top surface are preferably curved (hereinafter such a curved shape is also referred to as a rounded shape). The radius of curvature of the curved surface at an end portion of the conductor layer 242B is greater than or equal to 3 nm and less than or equal to 10 nm, preferably greater than or equal to 5 nm and less than or equal to 6 nm, for example. When the end portions are not angular, the coverage with films deposited in a later step can be improved.

Note that for the processing of the oxide films and the conductive film, a lithography method can be employed. The processing can be performed by a dry etching method or a wet etching method. The processing by a dry etching method is suitable for microfabrication.

Next, an insulating film 272A is deposited over the insulator 224, the oxide 230 a, the oxide 230 b, the oxide layer 243B, and the conductor layer 242B (see FIG. 6).

The insulating film 272A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 272A, an insulating film having a function of inhibiting the transmission of oxygen is preferably used. For example, silicon nitride or silicon oxide is deposited by a sputtering method.

Then, an insulating film 273A is deposited over the insulating film 272A. The insulating film 273A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, an aluminum oxide film is preferably deposited by a sputtering method. In this embodiment, an aluminum oxide film is deposited by a sputtering method (see FIG. 6).

Next, an insulating film to be the insulator 280 is deposited over the insulating film 273A. The insulating film to be the insulator 280 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, the insulating film to be the insulator 280 is subjected to CMP treatment, so that the insulator 280 having a flat top surface is formed (see FIG. 7).

Then, part of the insulator 280, part of the insulating film 273A, part of the insulating film 272A, the oxide layer 243B, and part of the conductor layer 242B are processed to form an opening reaching the oxide 230 b. The opening is preferably formed to overlap with the conductor 205. The oxide 243 a, the oxide 243 b, the conductor 242 a, the conductor 242 b, the insulator 272, and the insulator 273 are formed by the formation of the opening (see FIG. 7).

Part of the insulator 280, part of the insulating film 273A, part of the insulating film 272A, the oxide layer 243B, and part of the conductor layer 242B may be processed under different conditions. For example, part of the insulator 280 may be processed by a dry etching method, part of the insulating film 273A may be processed by a wet etching method, and part of the insulating film 272A, the oxide layer 243B, and part of the conductor layer 242B may be processed by a dry etching method.

In some cases, the treatment such as dry etching causes the attachment or diffusion of impurities due to an etching gas or the like to a surface or an inside of the oxide 230 a, the oxide 230 b, or the like. Examples of the impurities include fluorine and chlorine.

In order to remove the above impurities and the like, cleaning is performed. Examples of the cleaning method include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and any of these cleanings may be performed in appropriate combination.

The wet cleaning may be performed using an aqueous solution in which oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, or the like is diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.

Next, heat treatment may be performed. Heat treatment may be performed under reduced pressure, and an oxide film 230C may be successively deposited without exposure to the air. The treatment can remove moisture and hydrogen adsorbed onto the surface of the oxide 230 b and the like, and further can reduce the moisture concentration and the hydrogen concentration of the oxide 230 a and the oxide 230 b. The heat treatment is preferably performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. In this embodiment, the heat treatment is performed at 200° C. (see FIG. 8).

It is preferable that the oxide film 230C be provided in contact with at least part of the side surface of the oxide 230 a, part of the top and side surfaces of the oxide 230 b, part of the side surfaces of the oxide 243, part of the side surfaces of the conductor 242, the side surfaces of the insulator 272, the side surfaces of the insulator 273, and the side surfaces of the insulator 280. When the conductor 242 is surrounded by the oxide 243, the insulator 272, and the oxide film 230C, a decrease in the conductivity of the conductor 242 due to oxidation in a later step can be inhibited.

The oxide film 230C can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C is deposited by a method similar to that for the oxide film to be the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide film 230C. In this embodiment, the oxide film 230C is deposited by a sputtering method using a target with In:Ga:Zn=1:3:4 [atomic ratio] or In:Ga:Zn=4:2:4.1 [atomic ratio].

The oxide film 230C may have a stacked-layer structure. For example, the oxide film 230C may be deposited by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] and successively deposited using a target of In:Ga:Zn=1:3:4 [atomic ratio].

In particular, when the oxide film 230C is deposited, part of oxygen included in the sputtering gas is supplied to the oxide 230 a and the oxide 230 b in some cases. Therefore, the proportion of oxygen included in the sputtering gas for the oxide film 230C is preferably 70% or higher, further preferably 80% or higher, and still further preferably 100%.

Next, heat treatment may be performed. Heat treatment may be performed under reduced pressure, and the insulating film 250A may be successively deposited without exposure to the air. The treatment can remove moisture and hydrogen adsorbed onto the surface of the oxide film 230C and the like, and further can reduce the moisture concentration and the hydrogen concentration of the oxide 230 a, the oxide 230 b, and the oxide film 230C. The heat treatment is preferably performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. (see FIG. 9).

The insulating film 250A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulating film 250A, silicon oxynitride is preferably deposited by a CVD method. Note that the deposition temperature at the time of the deposition of the insulating film 250A is preferably higher than or equal to 350° C. and lower than 450° C., particularly preferably approximately 400° C. When the insulating film 250A is deposited at 400° C., an insulator having few impurities can be deposited.

Next, the conductive film 260Aa and the conductive film 260Ab are deposited. The conductive film 260Aa and the conductive film 260Ab can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a CVD method is preferably used. In this embodiment, the conductive film 260Aa is deposited by an ALD method, and the conductive film 260Ab is deposited by a CVD method (see FIG. 10).

Then, the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and the conductive film 260Ab are polished by CMP treatment until the insulator 280 is exposed, whereby the oxide 230 c, the insulator 250, and the conductor 260 (the conductor 260 a and the conductor 260 b) are formed (see FIG. 11).

Since the conductor 242 is provided to be surrounded by the oxide 243, the insulator 272, and the oxide 230 c, a decrease in the conductivity of the conductor 242 due to oxidation can be inhibited.

Next, heat treatment may be performed. In this embodiment, the treatment is performed at 400° C. in a nitrogen atmosphere for an hour. The heat treatment can reduce the moisture concentration and the hydrogen concentration in the insulator 250 and the insulator 280.

Next, an insulating film to be the insulator 282 may be formed over the conductor 260, the oxide 230 c, the insulator 250, and the insulator 280. The insulating film to be the insulator 282 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An aluminum oxide is preferably deposited as the insulating film to be the insulator 282 by a sputtering method, for example. It is preferable to form the insulator 282 in contact with the top surface of the conductor 260 in this manner because oxygen included in the insulator 280 can be inhibited from being absorbed into the conductor 260 in a later heat treatment (see FIG. 11).

Next, heat treatment may be performed. In this embodiment, the treatment is performed at 400° C. in a nitrogen atmosphere for an hour. By the heat treatment, oxygen added by the deposition of the insulator 282 can be injected into the insulator 280. In addition, the oxygen can be injected into the oxide 230 a and the oxide 230 b through the oxide 230 c.

Next, an insulating film to be the insulator 274 may be deposited over the insulator 282. The insulating film to be the insulator 274 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 11).

Next, an insulating film to be the insulator 281 may be deposited over the insulator 274. An insulating film to be the insulator 281 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Silicon nitride is preferably deposited as the insulating film to be the insulator 281 by a sputtering method, for example (see FIG. 11).

Then, openings that reach the conductor 242 a and the conductor 242 b are formed in the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 274, and the insulator 281. The openings are formed by a lithography method.

Next, an insulating film to be the insulator 241 is deposited and the insulating film is subjected to anisotropic etching, so that the insulator 241 is formed. The conducting film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 241, an insulating film having a function of inhibiting transmission of oxygen is preferably used. For example, aluminum oxide or silicon nitride is preferably deposited by an ALD method. For the anisotropic etching, a dry etching method or the like is performed, for example. When the side wall portions of the openings have such a structure, transmission of oxygen from the outside can be inhibited and oxidation of the formed conductor 240 a and conductor 240 b can be prevented. Furthermore, impurities such as water and hydrogen can be prevented from diffused from the conductor 240 a and the conductor 240 b to the outside.

Next, a conductive film to be the conductor 240 a and the conductor 240 b is deposited. The conductive film to be the conductor 240 a and the conductor 240 b desirably has a stacked-layer structure which includes a conductor having a function of inhibiting transmission of impurities such as water and hydrogen. For example, a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be employed. The conductive film to be the conductor 240 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, CMP treatment is performed to remove part of the conductive film to be the conductor 240 a and the conductor 240 b, so that the insulator 281 is exposed. As a result, the conductive film remains only in the openings, so that the conductor 240 a and the conductor 240 b having planar top surfaces can be formed (see FIG. 1). Note that the insulator 281 is partly removed by the CMP treatment in some cases.

Next, a conductive film to be the conductor 246 is deposited. The conductive film to be the conductor 246 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film to be the conductor 246 is processed by a lithography method to form the conductor 246 a in contact with the top surface of the conductor 240 a and the conductor 246 b in contact with the top surface of the conductor 240 b (see FIG. 1).

Through the above process, the semiconductor device including the transistor 200 illustrated in FIG. 1 can be fabricated. As illustrated in FIG. 4 to FIG. 11, with the use of the method of manufacturing the semiconductor device described in this embodiment, the transistor 200 can be fabricated.

Modification Example

An example of a semiconductor device including the transistor 200 of one embodiment of the present invention which is different from the semiconductor device described in <Structure example of semiconductor device> above will be described below with reference to FIG. 13 and FIG. 15. Note that in the semiconductor device illustrated in FIG. 13 and FIG. 15, structures having the same functions as the structures in the semiconductor device described in <Structure example of semiconductor device> (see FIG. 1) are denoted by the same reference numerals. Note that the materials described in detail in <Structure example of semiconductor device> can be used as constituent materials of the semiconductor devices in this section.

FIGS. 13(A), 13(B), and 13(C) are a top view and cross-sectional views of the transistor 200 of one embodiment of the present invention and the periphery of the transistor 200.

FIG. 13(A) is a top view of a semiconductor device including the transistor 200. FIG. 13(B) and FIG. 13(C) are cross-sectional views of the semiconductor device. Here, FIG. 13(B) is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 13(A), and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 13(C) is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 1(A), and is also a cross-sectional view in the channel width direction of the transistor 200. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 13(A).

Although the structure of the modification example of the semiconductor device of one embodiment of the present invention is similar to the structure of the semiconductor device in FIG. 1, the structure of the transistor 200 is different.

[Transistor 200]

As illustrated in FIG. 13, the transistor 200 includes an insulator 216 over the insulator 214; a conductor 205 (a conductor 205 a and a conductor 205 b) disposed so as to be embedded in the insulator 216; an insulator 222 over the insulator 216 and the conductor 205; an insulator 224 over the insulator 222; an oxide 230 a over the insulator 224; an oxide 230 b over the oxide 230 a; an oxide 243 a and an oxide 243 b over the oxide 230 b; a conductor 242 a over the oxide 243 a; a conductor 242 b over the oxide 243 b; an oxide 230 c over the oxide 230 b; an insulator 250 over the oxide 230 c; a conductor 260 (a conductor 260 a and a conductor 260 b) positioned over the insulator 250 and overlapping with the oxide 230 c; an insulator 272 in contact with part of a top surface of the insulator 224, a side surface of the oxide 230 a, a side surface of the oxide 230 b, a side surface of the oxide 243 a, a side surface of the oxide 243 b, a side surface of the conductor 242 a, a top surface of the conductor 242 a, a side surface of the conductor 242 b, and a top surface of the conductor 242 b; and an insulator 273 over the insulator 272. The oxide 230 c is in contact with a side surface of the oxide 243 a and a top surface of a region of the oxide 243 a not overlapping with the conductor 242 a and a side surface of the oxide 243 b and a top surface of a region of the oxide 243 b not overlapping with the conductor 242 b. The conductor 260 includes the conductor 260 a and the conductor 260 b, and the conductor 260 a is positioned so as to cover a bottom surface and a side surface of the conductor 260 b. Here, as illustrated in FIG. 13(B), a top surface of the conductor 260 is disposed to be substantially aligned with a top surface of the insulator 250 and a top surface of the oxide 230 c. The insulator 282 is in contact with a top surface of each of the conductor 260, the oxide 230 c, the insulator 250, and the insulator 280.

As described above, the oxide 243 a has a region not overlapping with the conductor 242 a, and the oxide 243 b has a region not overlapping with the conductor 242 b. That is, the oxide 243 a and the oxide 243 b are provided so as to have a portion that protrudes into an opening provided in the insulator 280.

It is preferable that the insulator 222, the insulator 272, the insulator 273, and the insulator 282 have a function of inhibiting diffusion of hydrogen (e.g., at least one of a hydrogen atom, a hydrogen molecule, and the like). In addition, it is preferable that the insulator 222, the insulator 272, the insulator 273, and the insulator 282 have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). For example, it is preferable that the insulator 222, the insulator 272, the insulator 273, and the insulator 282 each have a lower permeability of one or both of oxygen and hydrogen than the insulator 224. It is preferable that the insulator 222, the insulator 272, the insulator 273, and the insulator 282 each have a lower permeability of one or both of oxygen and hydrogen than the insulator 250. It is preferable that the insulator 222, the insulator 272, the insulator 273, and the insulator 282 each have a lower permeability of one or both of oxygen and hydrogen than the insulator 280.

As illustrated in FIG. 13(B), the insulator 272 is preferably in contact with the top surface and side surface of the conductor 242 a, the top surface and side surface of the conductor 242 b, the side surfaces of the oxide 243 a, the side surface of the oxide 243 b, the side surface of the oxide 230 a, the side surface of the oxide 230 b, and the top surface of the insulator 224. The insulator 273 is preferably provided over and in contact with the insulator 272. Thus, the insulator 280 is isolated from the insulator 224 and the oxide 230 by the insulator 272 and the insulator 273.

The oxide 230 preferably includes the oxide 230 a placed over the insulator 224, the oxide 230 b placed over the oxide 230 a, and the oxide 230 c which is placed over the oxide 230 b and at least partly in contact with a top surface of the oxide 230 b.

The transistor 200 has, in the region where a channel is formed (hereinafter also referred to as a channel formation region) and its vicinity, a structure in which three layers of the oxide 230 a, the oxide 230 b, and the oxide 230 c are stacked; however, the present invention is not limited thereto. For example, a structure may be employed in which a single-layer structure of the oxide 230 b, a two-layer structure of the oxide 230 b and the oxide 230 a, a two-layer structure of the oxide 230 b and the oxide 230 c, or a stacked-layer structure of four or more layers is provided. Although the transistor 200 with a structure in which the conductor 260 has a stacked-layer structure of two layers is described, the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked-layer structure of three or more layers.

The oxide 243 (the oxide 243 a and the oxide 243 b) preferably has conductivity. The oxide 243 and the conductor 242 (the conductor 242 a and the conductor 242 b) function as a source electrode or a drain electrode. When the oxide 243 which has conductivity is provided between the conductor 242 and the oxide 230 b, the electrical resistance between the conductor 242 and the oxide 230 b is reduced, which is preferable. Such a structure improves the electrical characteristics and reliability of the transistor 200. The oxide 243 may have a crystalline structure.

For the oxide 243, an oxide containing zinc can be used. For example, zinc oxide, gallium zinc oxide, indium zinc oxide, or indium gallium zinc oxide can be used. Alternatively, indium oxide or indium tin oxide may be used. The oxide 243 is preferably a metal oxide having high bond energy between a metal atom and an oxygen atom. The conductivity of the oxide 243 is preferably higher than that of the oxide 230 (the oxide 230 a, the oxide 230 b, and the oxide 230 c). The thickness of the oxide 243 is preferably greater than or equal to 1 nm and less than or equal to 10 nm, further preferably greater than or equal to 1 nm and less than or equal to 5 nm. The oxide 243 preferably has crystallinity. The oxide 243 with crystallinity efficiently inhibits release of oxygen from the oxide 230. When the oxide 243 has a hexagonal crystal structure, for example, release of oxygen from the oxide 230 can sometimes be inhibited.

Here, the conductor 260 functions as a gate electrode of the transistor and the oxide 243 a, the oxide 243 b, the conductor 242 a, and the conductor 242 b each function as a source electrode or a drain electrode. In the transistor 200, the conductor 260 functioning as the gate electrode is formed in a self-aligned manner to fill an opening formed in the insulator 280 and the like. The formation of the conductor 260 in this manner allows the conductor 260 to be surely placed in a region between the conductor 242 a and the conductor 242 b without alignment.

FIG. 15 is an enlarged view of the vicinity of the channel formation region of the transistor 200 in FIG. 13(B). As illustrated in FIG. 15, the facing side surfaces of the oxide 243 a and the oxide 243 b are provided on an inner side than the facing side surfaces of the conductor 242 a and the conductor 242 b. Thus, the distance between the source electrode and the drain electrode of the transistor 200, that is, the length of the channel length (L) is determined by the distance between the oxide 243 a and the oxide 243 b. The distance between the oxide 243 a and the oxide 243 b can be shorter than the width of the opening provided in the insulator 280 and than the distance between the conductor 242 a and the conductor 242 b. That is, the opening provided in the insulator 280 can be formed large; thus, the oxide 230 c, the insulator 250, and the conductor 260 can be easily embedded even when the channel length of the transistor 200 is short.

For example, in the case where the channel length (L) of the transistor 200 is 20 nm, if the width of a region of the oxide 243 not overlapping with the conductor 242 can be 20 nm, the width of the opening formed in the insulator 280 can be 60 nm. Similarly, if the width of the region of the oxide 243 not overlapping with the conductor 242 can be 5 nm, the width of the opening formed in the insulator 280 can be 30 nm. In addition, part of the oxide 243 and part of the conductor 260 can overlap with each other. For example, in the case where the length (L′) between the conductor 242 a and the conductor 242 b illustrated in FIG. 15 is 60 nm, the length of the channel length (L) can be less than 60 nm, preferably less than or equal to 30 nm, more preferably greater than or equal to 5 nm and less than or equal to 10 nm.

In the oxide 230 b, a region 234 functions as a channel formation region, a region 231 a functions as one of a source region and a drain region, and a region 231 b functions as the other of the source region and the drain region.

The semiconductor device illustrated in FIG. 1 can be referred to for the other structures and the effect.

<Method of Fabricating Modification Example>

Next, a method of fabricating a modification example of a semiconductor device including the transistor 200, which is illustrated in FIG. 13, will be described with reference to FIG. 16 to FIG. 24. In FIG. 16 to FIG. 24, (A) of each drawing is a top view. Moreover, (B) of each drawing is a cross-sectional view corresponding to a portion indicated by the dashed-dotted line A1-A2 in (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Furthermore, (C) of each drawing is a cross-sectional view corresponding to a portion indicated by the dashed-dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. Note that for simplification of the drawings, some components are not illustrated in the top view of (A) of each drawing.

FIG. 14 illustrates an example of a semiconductor device in which the conductor 205 and the insulator 216 are formed by a different method, as in the semiconductor device illustrated in FIG. 2.

For the formation of the modification example, the steps up to forming the insulator 280 over the insulating film 273A are similar to the method of forming the semiconductor device illustrated in FIG. 1, and <Manufacturing method of semiconductor device> can be referred to.

After the formation of the insulator 280, part of the insulator 280, part of the insulating film 273A, part of the insulating film 272A, and part of the conductor layer 242B are processed to form an opening from which the oxide layer 243B is exposed. The opening is preferably formed to overlap with the conductor 205. The conductor 242 a, the conductor 242 b, the insulator 272, and the insulator 273 are formed by the formation of the opening. In addition, formation of the opening decreases the thickness of part of the oxide layer 243B in some cases (see FIG. 16).

Part of the insulator 280, part of the insulating film 273A, part of the insulating film 272A, and part of the conductor layer 242B may be processed under different conditions. For example, part of the insulator 280 may be processed by a dry etching method, part of the insulating film 273A may be processed by a wet etching method, and part of the insulating film 272A and part of the conductor layer 242B may be processed by a dry etching method.

Next, a dummy film 265A is formed over the insulator 280 and inside the opening (see FIG. 17). The dummy film 265A needs to be formed on a sidewall of the opening; the distance between the oxide 243 a and the oxide 243 b, that is, the channel length (L) is determined by the thickness of the dummy film. Thus, the dummy film 265A is preferably formed by a CVD method or an ALD method that provides good coverage and makes fine adjustment of the thickness comparatively easily. The dummy film 265A may be formed so as to have a thickness on the sidewall of the opening of greater than or equal to 5 nm and less than or equal to 20 nm, and the thickness may be set as appropriate depending on electrical characteristics required for the transistor 200. For example, in the case where the dummy film 265A on the sidewall of the opening is 5 nm, the channel length can be shorter than the width of the opening by 10 nm, and in the case where the thickness of the dummy film 265A on the sidewall of the opening is 20 nm, the channel length can be shorter than the width of the opening by 40 nm. Note that a film that can be easily processed minutely and easily removed is preferably used as the dummy film 265A because the dummy film 265A is finally removed.

Next, the dummy film 265A is subjected to anisotropic etching so that only a portion of the dummy film 265A which is in contact with the sidewall of the opening is left, whereby a dummy film 265 is formed (see FIG. 18). At this time, the width of the dummy film 265 is preferably greater than or equal to 5 nm and less than or equal to 20 nm. The width of the dummy film 265 depends on the thickness of the dummy film 265A on the sidewall of the opening. In the case where the width of the dummy film 265 is shorter than the thickness of the dummy film 265A on the sidewall of the opening, the dummy film 265A may be formed thicker and the thickness is not limited to the above-described values.

Next, the oxide layer 243B is etched using the dummy film 265 as a mask, whereby the oxide 243 a and the oxide 243 b are formed (see FIG. 19). Note that etching of the dummy film 265 and etching of the oxide layer 243B may be performed successively. Furthermore, in some cases, the top surface of the oxide 230 b that is exposed between the oxide 243 a and the oxide 243 b is partly removed.

At this time, the oxide layer 243B is processed using the dummy film 265 as a mask, whereby the oxide 243 a and the oxide 243 b are formed. Thus, the opening formed in the insulator 280 overlaps with a region between the conductor 242 a and the conductor 242 b and a region between the oxide 243 a and the oxide 243 b. In this manner, the conductor 260 can be positioned between the conductor 242 a and the conductor 242 b and between the oxide 243 a and the oxide 243 b in a self-aligned manner in a later step.

Note that in this embodiment, the method of forming the oxide layer 243B using the dummy film 265 is described; however, the method is not limited to this. For example, after the oxide layer 243B is formed, a resist mask or the like may be formed by a lithography method and the oxide layer 243B may be processed using the resist mask, whereby the oxide 243 a and the oxide 243 b are formed.

Then, the dummy film 265 is selectively removed by isotropic etching (see FIG. 20). As the isotropic etching, wet etching or etching using a reactive gas is used, for example. In this manner, the distance between the oxide 243 a and the oxide 243 b can be shorter than the length of the opening in the channel length direction.

In some cases, the treatment such as dry etching causes the attachment or diffusion of impurities due to an etching gas or the like to a surface or an inside of the oxide 230 a, the oxide 230 b, or the like. Examples of the impurities include fluorine and chlorine.

In order to remove the above impurities and the like, cleaning is performed. Examples of the cleaning method include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and any of these cleanings may be performed in appropriate combination.

The wet cleaning may be performed using an aqueous solution in which oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, or the like is diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.

Next, heat treatment may be performed. Heat treatment may be performed under reduced pressure, and an oxide film 230C may be successively deposited without exposure to the air. The treatment can remove moisture and hydrogen adsorbed onto the surface of the oxide 230 b and the like, and further can reduce the moisture concentration and the hydrogen concentration of the oxide 230 a and the oxide 230 b. The heat treatment is preferably performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. In this embodiment, the heat treatment is performed at 200° C. (see FIG. 21).

It is preferable that the oxide film 230C be provided in contact with at least part of the side surface of the oxide 230 a, part of the top and side surfaces of the oxide 230 b, part of the side surfaces of the oxide 243, a top surface of a region of the oxide 243 not overlapping with the conductor 242, part of the side surfaces of the conductor 242, the side surfaces of the insulator 272, the side surfaces of the insulator 273, and the side surfaces of the insulator 280. When the conductor 242 is surrounded by the oxide 243, the insulator 272, and the oxide film 230C, a decrease in the conductivity of the conductor 242 due to oxidation in a later step can be inhibited.

The oxide film 230C can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C is deposited by a method similar to that for the oxide film to be the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide film 230C. In this embodiment, the oxide film 230C is deposited by a sputtering method using a target with In:Ga:Zn=1:3:4 [atomic ratio] or In:Ga:Zn=4:2:4.1 [atomic ratio].

The oxide film 230C may have a stacked-layer structure. For example, the oxide film 230C may be deposited by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] and successively deposited using a target of In:Ga:Zn=1:3:4 [atomic ratio].

In particular, when the oxide film 230C is deposited, part of oxygen included in the sputtering gas is supplied to the oxide 230 a and the oxide 230 b in some cases. Therefore, the proportion of oxygen included in the sputtering gas for the oxide film 230C is preferably 70% or higher, further preferably 80% or higher, and still further preferably 100%.

Next, heat treatment may be performed. Heat treatment may be performed under reduced pressure, and the insulating film 250A may be successively deposited without exposure to the air. The treatment can remove moisture and hydrogen adsorbed onto the surface of the oxide film 230C and the like, and further can reduce the moisture concentration and the hydrogen concentration of the oxide 230 a, the oxide 230 b, and the oxide film 230C. The heat treatment is preferably performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. (see FIG. 22).

The insulating film 250A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulating film 250A, silicon oxynitride is preferably deposited by a CVD method. Note that the deposition temperature at the time of the deposition of the insulating film 250A is preferably higher than or equal to 350° C. and lower than 450° C., particularly preferably approximately 400° C. When the insulating film 250A is deposited at 400° C., an insulator having few impurities can be deposited.

Next, the conductive film 260Aa and the conductive film 260Ab are deposited. The conductive film 260Aa and the conductive film 260Ab can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a CVD method is preferably used. In this embodiment, the conductive film 260Aa is deposited by an ALD method, and the conductive film 260Ab is deposited by a CVD method (see FIG. 23).

Then, the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and the conductive film 260Ab are polished by CMP treatment until the insulator 280 is exposed, whereby the oxide 230 c, the insulator 250, and the conductor 260 (the conductor 260 a and the conductor 260 b) are formed (see FIG. 24).

Since the conductor 242 is provided to be surrounded by the oxide 243, the insulator 272, and the oxide 230 c, a decrease in the conductivity of the conductor 242 due to oxidation can be inhibited.

Next, heat treatment may be performed. In this embodiment, the treatment is performed at 400° C. in a nitrogen atmosphere for an hour. The heat treatment can reduce the moisture concentration and the hydrogen concentration in the insulator 250 and the insulator 280.

Next, an insulating film to be the insulator 282 may be formed over the conductor 260, the oxide 230 c, the insulator 250, and the insulator 280. The insulating film to be the insulator 282 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An aluminum oxide is preferably deposited as the insulating film to be the insulator 282 by a sputtering method, for example. It is preferable to form the insulator 282 in contact with the top surface of the conductor 260 in this manner because oxygen included in the insulator 280 can be inhibited from being absorbed into the conductor 260 in a later heat treatment (see FIG. 24).

Next, heat treatment may be performed. In this embodiment, the treatment is performed at 400° C. in a nitrogen atmosphere for an hour. By the heat treatment, oxygen added by the deposition of the insulator 282 can be injected into the insulator 280. In addition, the oxygen can be injected into the oxide 230 a and the oxide 230 b through the oxide 230 c.

Next, an insulating film to be the insulator 274 may be deposited over the insulator 282. The insulating film to be the insulator 274 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 24).

Next, an insulating film to be the insulator 281 may be deposited over the insulator 274. An insulating film to be the insulator 281 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Silicon nitride is preferably deposited as the insulating film to be the insulator 281 by a sputtering method, for example (see FIG. 24).

Then, openings that reach the conductor 242 a and the conductor 242 b are formed in the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 274, and the insulator 281. The openings are formed by a lithography method.

Next, an insulating film to be the insulator 241 is deposited and the insulating film is subjected to anisotropic etching, so that the insulator 241 is formed. The conducting film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 241, an insulating film having a function of inhibiting transmission of oxygen is preferably used. For example, aluminum oxide or silicon nitride is preferably deposited by an ALD method. For the anisotropic etching, a dry etching method or the like is performed, for example. When the side wall portions of the openings have such a structure, transmission of oxygen from the outside can be inhibited and oxidation of the formed conductor 240 a and conductor 240 b can be prevented. Furthermore, impurities such as water and hydrogen can be prevented from diffused from the conductor 240 a and the conductor 240 b to the outside.

Next, a conductive film to be the conductor 240 a and the conductor 240 b is deposited. The conductive film to be the conductor 240 a and the conductor 240 b desirably has a stacked-layer structure which includes a conductor having a function of inhibiting transmission of impurities such as water and hydrogen. For example, a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be employed. The conductive film to be the conductor 240 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, CMP treatment is performed to remove part of the conductive film to be the conductor 240 a and the conductor 240 b, so that the insulator 281 is exposed. As a result, the conductive film remains only in the openings, so that the conductor 240 a and the conductor 240 b having planar top surfaces can be formed (see FIG. 13). Note that the insulator 281 is partly removed by the CMP treatment in some cases.

Next, a conductive film to be the conductor 246 is deposited. The conductive film to be the conductor 246 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film to be the conductor 246 is processed by a lithography method to form the conductor 246 a in contact with the top surface of the conductor 240 a and the conductor 246 b in contact with the top surface of the conductor 240 b (see FIG. 13).

Through the above process, the modification example of the semiconductor device including the transistor 200 illustrated in FIG. 13 can be fabricated.

According to one embodiment of the present invention, a semiconductor device having a high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having excellent frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high productivity can be provided.

The structure, method, and the like described above in this embodiment can be used in combination as appropriate with the structures, methods, and the like described in the other embodiments and the examples.

Embodiment 2

In this embodiment, one embodiment of a semiconductor device will be described with reference to FIG. 25 to FIG. 28.

[Memory Device 1]

FIG. 25 and FIG. 26 each illustrate an example of a semiconductor device (a memory device) using a capacitor of one embodiment of the present invention. Note that FIG. 26 illustrates an example of a semiconductor device (a memory device) using the transistor 200 described in Modification example. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, a memory device which is the transistor 200 can retain stored data for a long time. In other words, such a memory device does not require refresh operation or has an extremely low frequency of the refresh operation, which leads to a sufficient reduction in power consumption of the memory device.

In the semiconductor device illustrated in FIG. 25 and FIG. 26, a wiring 1001 is electrically connected to a source of the transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and the drain of the transistor 200. A wiring 1004 is electrically connected to a first gate of the transistor 200. A wiring 1006 is electrically connected to a second gate of the transistor 200. A gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one electrode of the capacitor 100. A wiring 1005 is electrically connected to the other electrode of the capacitor 100.

The memory devices illustrated in FIG. 25 and FIG. 26 can form a memory cell array when arranged in a matrix.

<Transistor 300>

The transistor 300 is provided over a substrate 311 and includes a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314 a and a low-resistance region 314 b functioning as the source region and the drain region. The transistor 300 may be a p-channel type or an n-channel type.

In the transistor 300 illustrated in FIG. 25 and FIG. 26, the semiconductor region 313 (part of the substrate 311) in which a channel is formed has a convex shape. Furthermore, the conductor 316 is provided to cover top and side surfaces of the semiconductor region 313 with the insulator 315 therebetween. Note that a material adjusting the work function may be used for the conductor 316. The transistor 300 having such a structure is also referred to as a FIN transistor because the projecting portion of the semiconductor substrate is utilized. An insulator functioning as a mask for forming the projecting portion may be included in contact with the top surface of the projecting portion. Although the case where the projecting portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a projecting shape may be formed by processing an SOI substrate.

Note that the transistor 300 illustrated in FIG. 25 and FIG. 26 is an example and the structure is not limited thereto; an appropriate transistor is used in accordance with a circuit configuration or a driving method.

<Capacitor 100>

The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.

For example, a conductor 112 and the conductor 110 over the conductor 246 can be formed at the same time. Note that the conductor 112 functions as a plug or a wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

Although the conductor 112 and the conductor 110 having a single-layer structure are illustrated in FIG. 25 and FIG. 26, the structure is not limited thereto; a stacked-layer structure of two or more layers may be employed. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor which is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed.

For the insulator 130, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like is used, and a stacked layer or a single layer can be provided.

For example, for the insulator 130, a stacked-layer structure using a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material is preferably used. In the capacitor 100 having such a structure, a sufficient capacitance can be ensured owing to the high dielectric constant (high-k) insulator, and the dielectric strength can be increased owing to the insulator with high dielectric strength, so that the electrostatic breakdown of the capacitor 100 can be inhibited.

As the insulator of a high dielectric constant (high-k) material (a material having a high dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, an oxide including silicon and hafnium, an oxynitride including silicon and hafnium, a nitride including silicon and hafnium, or the like can be given.

As the material having a high dielectric strength (a material having a low dielectric constant), silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like can be given.

<Wiring Layers>

Wiring layers provided with an interlayer film, a wiring, a plug, and the like may be provided between the structure bodies. A plurality of wiring layers can be provided in accordance with the design. Here, a plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, part of a conductor functions as a wiring in some cases and part of a conductor functions as a plug in other cases.

For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked over the transistor 300 in this order as interlayer films. A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductor 328 and the conductor 330 each function as a plug or a wiring.

The insulator functioning as an interlayer film may function as a planarization film that covers a roughness thereunder. For example, a top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 25 and FIG. 26, an insulator 350, an insulator 352, and an insulator 354 are stacked sequentially. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

Similarly, a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 functions as a plug or a wiring that is electrically connected to the capacitor 100 or the transistor 300. In addition, an insulator 150 is provided over the conductor 120 and the insulator 130.

As an insulator that can be used as an interlayer film, an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, an insulating metal nitride oxide, or the like is given.

For example, when a material having a low dielectric constant is used for the insulator functioning as an interlayer film, the parasitic capacitance between wirings can be reduced. Accordingly, a material is preferably selected in accordance with the function of an insulator.

For example, for the insulator 150, the insulator 212, the insulator 352, the insulator 354, or the like, an insulator having a low dielectric constant is preferably used. For example, the insulator preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. Alternatively, the insulator preferably has a stacked-layer structure of a resin and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. Because silicon oxide and silicon oxynitride have thermal stability, a combination of silicon oxide or silicon oxynitride with a resin allows the stacked-layer structure to be thermally stable and have a low dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon and aramid), polyimide, polycarbonate, and acrylic.

When the transistor using an oxide semiconductor is surrounded by an insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stabilized. Thus, the insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen can be used for the insulator 210, the insulator 350, and the like.

The insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen can have, for example, a single-layer structure or a stacked-layer structure of an insulator including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, as the insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; silicon nitride oxide; silicon nitride; or the like can be used.

For the conductors that can be used for wirings or plugs, a material including one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor having a high electric conductivity typified by polycrystalline silicon including an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

For example, for the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like, a single-layer structure or a stacked-layer structure using a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material that is formed using the above materials can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

<Wirings or Plugs in Layer Provided with Oxide Semiconductor>

In the case where an oxide semiconductor is used in the transistor 200, an insulator including an excess oxygen region is provided in the vicinity of the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator including the excess oxygen region and the conductor provided in the insulator including the excess oxygen region.

For example, an insulator 276 is preferably provided between the insulator 224 including excess oxygen and a conductor 245 in FIG. 25 and FIG. 26. Since the insulator 276 is provided in contact with the insulator 222 and the insulator 272, the insulator 224 and the transistor 200 can be sealed by the insulators having a barrier property. It is preferable that the insulator 276 be also in contact with part of the insulator 280. When the insulator 276 extends to the insulator 280, diffusion of oxygen and impurities can be further inhibited.

That is, the insulator 276 can inhibit excess oxygen included in the insulator 224 from being absorbed by the conductor 245. In addition, the insulator 276 can inhibit diffusion of hydrogen, which is an impurity, into the transistor 200 through the conductor 245.

The insulator 276 is preferably formed using an insulating material having a function of inhibiting diffusion of an impurity such as water or hydrogen and oxygen. For example, aluminum oxide, hafnium oxide, or the like is preferably used. Other than that, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used, for example.

The above is the description of the structure example. With the use of the structure, a semiconductor device using a transistor including an oxide semiconductor can have a small variation in electrical characteristics and higher reliability. Alternatively, a transistor including an oxide semiconductor with a high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

[Memory Device 2]

FIG. 27 and FIG. 28 each illustrate an example of a memory device using the semiconductor device of one embodiment of the present invention. Note that FIG. 28 illustrates an example of a memory device using the transistor 200 described in Modification example. The memory device illustrated in FIG. 27 and FIG. 28 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG. 25 and FIG. 26.

The transistor 400 can change a second gate voltage of the transistor 200. For example, a first gate and a second gate of the transistor 400 are diode-connected to a source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When a negative potential of the second gate of the transistor 200 is held in this structure, a first gate-source voltage and a second gate-source voltage of the transistor 400 are 0 V. In the transistor 400, a drain current when the second gate voltage and the first gate voltage are 0 V is extremely low; thus, the negative potential of the second gate of the transistor 200 can be held for a long time even without power supply to the transistor 200 and the transistor 400. Accordingly, the memory device including the transistor 200 and the transistor 400 can retain stored data for a long time.

In FIG. 27 and FIG. 28, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to a back gate of the transistor 200. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one electrode of the capacitor 100. The wiring 1005 is electrically connected to the other electrode of the capacitor 100. A wiring 1007 is electrically connected to the source of the transistor 400. A wiring 1008 is electrically connected to a gate of the transistor 400. A wiring 1009 is electrically connected to a back gate of the transistor 400. A wiring 1010 is electrically connected to the drain of the transistor 400. The wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected to each other.

When the memory devices illustrated in FIG. 27 and FIG. 28 are arranged in a matrix like the memory devices illustrated in FIG. 25 and FIG. 26, a memory cell array can be formed. Note that one transistor 400 can change second gate voltages of a plurality of transistors 200. For this reason, the number of transistors 400 is preferably smaller than the number of transistors 200.

<Transistor 400>

The transistor 400 and the transistors 200 are formed in the same layer and thus can be fabricated in parallel. The transistor 400 includes a conductor 460 (a conductor 460 a and a conductor 460 b) functioning as a first gate electrode; a conductor 405 (a conductor 405 a and a conductor 405 b) functioning as a second gate electrode; the insulator 222, the insulator 224, and an insulator 450 functioning as a gate insulating layer; an oxide 430 c including a channel formation region; a conductor 442 a, an oxide 443 a, an oxide 431 a, and an oxide 431 b functioning as one of a source and a drain; a conductor 442 b, an oxide 443 b, an oxide 432 a, and an oxide 432 b functioning as the other of the source and the drain; and a conductor 440 (a conductor 440 a and a conductor 440 b).

In the transistor 400, the conductor 405 is in the same layer as the conductor 205. The oxide 431 a and the oxide 432 a are in the same layer as the oxide 230 a, and the oxide 431 b and the oxide 432 b are in the same layer as the oxide 230 b. The conductor 442 is in the same layer as the conductor 242. The oxide 443 is in the same layer as the oxide 243. The oxide 430 c is in the same layer as the oxide 230 c. The insulator 450 is in the same layer as the insulator 250. The conductor 460 is in the same layer as the conductor 260.

Note that the structure body in the same layer can be formed at the same time. For example, the oxide 430 c can be formed by processing an oxide film to be the oxide 230 c.

In the oxide 430 c functioning as an active layer of the transistor 400, oxygen vacancies and impurities such as hydrogen or water are reduced, as in the oxide 230 or the like. Accordingly, the threshold voltage of the transistor 400 can be higher than 0 V, an off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be extremely low.

<Dicing Line>

Here, a dicing line (referred to as a scribe line, a dividing line, or a cutting line in some cases) which is provided when a large-sized substrate is divided into semiconductor elements so that a plurality of semiconductor devices are each formed in a chip form is described below. Examples of a dividing method include the case where a groove (a dicing line) for dividing the semiconductor elements is formed on the substrate, and then the substrate is cut along the dicing line to divide (split) it into a plurality of semiconductor devices.

Here, for example, as illustrated in FIG. 27 and FIG. 28, it is preferable that a region in which the insulator 272 and the insulator 222 are in contact with each other be the dicing line. That is, an opening is provided in the insulator 224 in the vicinity of the region to be the dicing line that is provided in an outer edge of the transistor 400 and the memory cell including a plurality of transistors 200. The insulator 272 is provided to cover the side surface of the insulator 224.

That is, in the opening provided in the insulator 224, the insulator 222 is in contact with the insulator 272. For example, the insulator 222 and the insulator 272 may be formed using the same material and the same method. When the insulator 222 and the insulator 272 are formed using the same material and the same method, the adhesion therebetween can be increased. For example, aluminum oxide is preferably used.

With such a structure, the insulator 224, the transistor 200 and the transistor 400 can be enclosed with the insulator 222 and the insulator 272. Since the insulator 222 and the insulator 272 have a function of inhibiting diffusion of oxygen, hydrogen, and water even when the substrate is divided into circuit regions each of which is provided with the semiconductor elements in this embodiment to form a plurality of chips, the mixing and diffusion of impurities such as hydrogen or water from the direction of a side surface of the divided substrate to the transistor 200 or the transistor 400 can be inhibited.

In the structure, excess oxygen in the insulator 224 can be inhibited from diffusing into the outside of the insulator 272 and the insulator 222. Accordingly, excess oxygen in the insulator 224 is efficiently supplied to the oxide where the channel is formed in the transistor 200 or the transistor 400. The oxygen can reduce oxygen vacancies in the oxide where the channel is formed in the transistor 200 or the transistor 400. Thus, the oxide where the channel is formed in the transistor 200 or the transistor 400 can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, the transistor 200 or the transistor 400 can have a small variation in the electrical characteristics and higher reliability.

This embodiment can be implemented in an appropriate combination with the structures described in the other embodiments, examples, and the like.

Embodiment 3

In this embodiment, a memory device of one embodiment of the present invention including a transistor in which an oxide is used for a semiconductor (hereinafter referred to as an OS transistor in some cases) and a capacitor (hereinafter, such a memory device is also referred to as an OS memory device in some cases), will be described with reference to FIG. 29 and FIG. 30. The OS memory device includes at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Since the OS transistor has an extremely low off-state current, the OS memory device has excellent retention characteristics and thus can function as a nonvolatile memory.

Structure Example of Memory Device

FIG. 29(A) illustrates a structure example of the OS memory device. A memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging wirings. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the wirings are connected to the memory cell included in the memory cell array 1470, and will be described later in detail. The amplified data signal is output as a data signal RDATA to the outside of the memory device 1400 through the output circuit 1440. The row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select a row to be accessed.

As power supply voltages from the outside, a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400. Control signals (CE, WE, and RE), an address signal ADDR, and a data signal WDATA are also input to the memory device 1400 from the outside. The address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.

The control logic circuit 1460 processes the input signals (CE, WE, and RE) input from the outside, and generates control signals for the row decoder and the column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. Signals processed by the control logic circuit 1460 are not limited thereto, and other control signals may be input as necessary.

The memory cell array 1470 includes a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of the wirings that connect the memory cell array 1470 to the row circuit 1420 depends on the structure of the memory cell MC, the number of the memory cells MC in a column, and the like. The number of the wirings that connect the memory cell array 1470 to the column circuit 1430 depends on the structure of the memory cell MC, the number of the memory cells MC in a row, and the like.

Note that FIG. 29(A) illustrates an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane; however, this embodiment is not limited thereto. For example, as illustrated in FIG. 29(B), the memory cell array 1470 may be provided to overlap part of the peripheral circuit 1411. For example, the sense amplifier may be provided below the memory cell array 1470 so that they overlap with each other.

FIG. 30 illustrates structure examples of a memory cell applicable to the memory cell MC.

[DOSRAM]

FIGS. 30(A) to 30(C) each illustrate a circuit structure example of a memory cell of a DRAM. In this specification and the like, a DRAM using a memory cell including one OS transistor and one capacitor is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) in some cases. A memory cell 1471 illustrated in FIG. 30(A) includes a transistor M1 and a capacitor CA. Note that the transistor M1 includes a gate (also referred to as a front gate in some cases) and a back gate.

A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA. A second terminal of the transistor M1 is connected to a wiring BIL. The gate of the transistor M1 is connected to a wiring WOL. The back gate of the transistor M1 is connected to a wiring BGL. A second terminal of the capacitor CA is connected to a wiring CAL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. In the time of data writing and data reading, a low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. Applying a given potential to the wiring BGL can increase or decrease the threshold voltage of the transistor M1.

The memory cell MC is not limited to the memory cell 1471, and the circuit structure can be changed. For example, as in a memory cell 1472 illustrated in FIG. 30(B), the back gate of the transistor M1 may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the memory cell MC may be a memory cell including a single-gate transistor, that is, the transistor M1 not including a back gate, as in a memory cell 1473 illustrated in FIG. 30(C).

In the case where the semiconductor device described in any of the above embodiments is used in the memory cell 1471 and the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. When an OS transistor is used as the transistor M1, the leakage current of the transistor M1 can be extremely low. That is, written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. In addition, refresh operation of the memory cell can be unnecessary. In addition, since the transistor M1 has an extremely low leakage current, multi-level data or analog data can be retained in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

In the DOSRAM, when the sense amplifier is provided below the memory cell array 1470 so that they overlap with each other as described above, the bit line can be shortened. Thus, the bit line capacitance can be small, and the storage capacitance of the memory cell can be reduced.

[NOSRAM]

FIGS. 30(D) to 30(H) each illustrate a circuit structure example of a gain-cell memory cell including two transistors and one capacitor. A memory cell 1474 illustrated in FIG. 30(D) includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 includes a front gate (simply referred to as a gate in some cases) and a back gate. In this specification and the like, a memory device including a gain-cell memory cell using an OS transistor as the transistor M2 is referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM) in some cases.

A first terminal of the transistor M2 is connected to a first terminal of the capacitor CB. A second terminal of the transistor M2 is connected to a wiring WBL. A gate of the transistor M2 is connected to the wiring WOL. A back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to a wiring RBL. A second terminal of the transistor M3 is connected to a wiring SL. A gate of the transistor M3 is connected to the first terminal of the capacitor CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. In the time of data writing, data retaining, and data reading, a low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By application of a given potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

The memory cell MC is not limited to the memory cell 1474, and the circuit structure can be changed as appropriate. For example, as in a memory cell 1475 illustrated in FIG. 30(E), the back gate of the transistor M2 may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the memory cell MC may be a memory cell including as single-gate transistor, that is, the transistor M2 not including a back gate, as in a memory cell 1476 illustrated in FIG. 30(F). Alternatively, for example, in the memory cell MC, the wiring WBL and the wiring RBL may be combined into one wiring BIL, as in a memory cell 1477 illustrated in FIG. 30(G).

In the case where the semiconductor device described in any of the above embodiments is used in the memory cell 1474 and the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. When an OS transistor is used as the transistor M2, the leakage current of the transistor M2 can be extremely low. That is, written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. In addition, refresh operation of the memory cell can be unnecessary. In addition, since the transistor M2 has an extremely low leakage current, multi-level data or analog data can be retained in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

Note that the transistor M3 may be a transistor containing silicon in a channel formation region (hereinafter, also referred to as a Si transistor in some cases). The conductivity type of the Si transistor may be of either an n-channel type or a p-channel type. The Si transistor has higher field-effect mobility than the OS transistor in some cases. Therefore, a Si transistor may be used as the transistor M3 functioning as a reading transistor. Furthermore, the transistor M2 can be provided to be stacked over the transistor M3 when a Si transistor is used as the transistor M3; therefore, the area occupied by the memory cell can be reduced, leading to high integration of the memory device.

Alternatively, the transistor M3 may be an OS transistor. When an OS transistor is used as each of the transistors M2 and M3, the circuit of the memory cell array 1470 can be formed using only n-channel transistors.

FIG. 30(H) illustrates an example of a gain-cell memory cell including three transistors and one capacitor. A memory cell 1478 illustrated in FIG. 30(H) includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to the wiring BIL, a wiring RWL, a wiring WWL, the wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring for supplying a low-level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.

The transistor M4 is an OS transistor including a back gate that is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not include the back gate.

Note that each of the transistors M5 and M6 may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors, in which case the circuit of the memory cell array 1470 can be formed using only n-channel transistors.

In the case where the semiconductor device described in any of the above embodiments is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. When an OS transistor is used as the transistor M4, the leakage current of the transistor M4 can be extremely low.

Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like described in this embodiment are not limited to the above. Positions and functions of these circuits, wirings connected to the circuits, circuit elements, and the like can be changed, deleted, or added as needed.

The structure described in this embodiment can be used in an appropriate combination with the structures described in the other embodiments, examples, and the like.

Embodiment 4

In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted will be described with reference to FIG. 31. A plurality of circuits (systems) are mounted on the chip 1200. The technique for integrating a plurality of circuits (systems) on one chip as described above is referred to as system on chip (SoC) in some cases.

As illustrated in FIG. 31(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more of analog arithmetic units 1213, one or more of memory controllers 1214, one or more of interfaces 1215, one or more of network circuits 1216, and the like.

A bump (not illustrated) is provided on the chip 1200, and as illustrated in FIG. 31(B), the chip 1200 is connected to a first surface of a printed circuit board (PCB) 1201. A plurality of bumps 1202 are provided on the rear side of the first surface of the PCB 1201, and the PCB 1201 is connected to a motherboard 1203.

A memory device such as a DRAM 1221 or a flash memory 1222 may be provided over the motherboard 1203. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. For example, the NOSRAM described in the above embodiment can be used as the flash memory 1222.

The CPU 1211 preferably includes a plurality of CPU cores. Furthermore, the GPU 1212 preferably includes a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each include a memory for storing data temporarily. Alternatively, a common memory for the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The NOSRAM or the DOSRAM described above can be used as the memory. The GPU 1212 is suitable for parallel computation of a number of data and thus can be used for image processing or product-sum operation. When an image processing circuit or a product-sum operation circuit including an oxide semiconductor of the present invention is provided in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.

In addition, since the CPU 1211 and the GPU 1212 are provided in the same chip, a wiring between the CPU 1211 and the GPU 1212 can be shortened; accordingly, the data transfer from the CPU 1211 to the GPU 1212, the data transfer between the memories included in the CPU 1211 and the GPU 1212, and the transfer of arithmetic operation results from the GPU 1212 to the CPU 1211 after the arithmetic operation in the GPU 1212 can be performed at high speed.

The analog arithmetic unit 1213 includes one or both of an A/D (analog/digital) converter circuit and a D/A (digital/analog) converter circuit. Furthermore, the analog arithmetic unit 1213 may include the above-described product-sum operation circuit.

The memory controller 1214 includes a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as the interface of the flash memory 1222.

The interface 1215 includes an interface circuit for connection with an external connection device such as a display device, a speaker, a microphone, a camera, or a controller. Examples of the controller include a mouse, a keyboard, and a game controller. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used.

The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). Furthermore, the network circuit 1216 may include a circuit for network security.

The circuits (systems) can be formed in the chip 1200 in the same manufacturing process. Therefore, even when the number of circuits needed for the chip 1200 is increased, there is no need to increase the number of steps in the manufacturing process; thus, the chip 1200 can be manufactured at low cost.

The motherboard 1203 provided with the PCB 1201 on which the chip 1200 including the GPU 1212 is mounted, the DRAM 1221, and the flash memory 1222 can be referred to as a GPU module 1204.

The GPU module 1204 includes the chip 1200 formed using the SoC technology, and thus can have a small size. Furthermore, the GPU module 1204 is excellent in image processing, and thus is suitably used in a portable electronic device such as a smartphone, a tablet terminal, a laptop PC, or a portable (mobile) game console. Furthermore, the product-sum operation circuit using the GPU 1212 can implement an arithmetic operation such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencorder, a deep Boltzmann machine (DBM), or a deep belief network (DBN); thus, the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.

The structure described in this embodiment can be used in an appropriate combination with the structures described in the other embodiments and other examples.

Embodiment 5

In this embodiment, application examples of the memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment can be applied to, for example, memory devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, the computers refer not only to tablet computers, notebook computers, and desktop computers, but also to large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment is applied to removable memory devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). FIG. 32 schematically illustrates some structure examples of removable memory devices. The semiconductor device described in the above embodiment is processed into a packaged memory chip and used in a variety of storage devices and removable memories, for example.

FIG. 32(A) is a schematic view of a USB memory. A USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is held in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like on the substrate 1104.

FIG. 32(B) is a schematic external view of an SD card, and FIG. 32(C) is a schematic view of the internal structure of the SD card. An SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is held in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. When the memory chip 1114 is also provided on the rear surface side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a radio communication function may be provided on the substrate 1113. With this, data can be read from and written in the memory chip 1114 by radio communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like on the substrate 1113.

FIG. 32(D) is a schematic external view of an SSD, and FIG. 32(E) is a schematic view of the internal structure of the SSD. An SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is held in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory for the controller chip 1156, and a DOSRAM chip may be used, for example. When the memory chip 1154 is also provided on the rear surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like on the substrate 1153.

This embodiment can be implemented in an appropriate combination with the structures described in the other embodiments, examples, and the like.

Embodiment 6

In this embodiment, a product image and specific examples of electronic devices that can be used for the semiconductor device of one embodiment of the present invention are described with reference to FIG. 33 and FIG. 34.

First, FIG. 33 illustrates a product image applicable to the semiconductor device of one embodiment of the present invention. A region 501 illustrated in FIG. 33 represents high temperature characteristics (High T operate), a region 502 represents high frequency characteristics (High f operate), a region 503 represents low off characteristics (Ioff), and a region 504 represents a region where the region 501, the region 502, and the region 503 overlap one another.

Note that when the region 501 is intended to be satisfied, it can be roughly satisfied by using a carbide or a nitride such as silicon carbide or gallium nitride for a channel formation region of a semiconductor device. When the region 502 is intended to be satisfied, it can be roughly satisfied by using a silicide such as single crystal silicon or crystalline silicon for a channel formation region of a semiconductor device. When the region 503 is intended to be satisfied, it can be roughly satisfied by using an oxide semiconductor or a metal oxide for a channel formation region of a semiconductor device.

The semiconductor device of one embodiment of the present invention can be favorably used for a product in the range represented by the region 504, for example.

A conventional product has difficulty in satisfying all of the region 501, the region 502, and the region 503. However, the semiconductor device of one embodiment of the present invention includes a crystalline OS in a channel formation region. In the case where the crystalline OS is included in the channel formation region, a semiconductor device and an electronic device which satisfy high temperature characteristics, high frequency characteristics, and low off characteristics can be provided.

Note that examples of a product in the range represented by the region 504 are an electronic device including a low-power consumption and high-performance CPU, an in-car electronic device required to have high reliability in a high-temperature environment, and the like.

Specifically, the semiconductor device of one embodiment of the present invention can be used for a processor such as a CPU and a GPU or a chip. FIG. 34 illustrates specific examples of electronic devices including a processor such as a CPU and a GPU or a chip of one embodiment of the present invention.

<Electronic Device and System>

The GPU or the computer of one embodiment of the present invention can be mounted on a variety of electronic devices. Examples of electronic devices include a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, and an audio reproducing device in addition to electronic devices provided with a relatively large screen, such as a television device, a desktop or laptop personal computer, a monitor for a computer and the like, digital signage, and a large game machine like a pachinko machine. In addition, when the integrated circuit or the chip of one embodiment of the present invention is provided in the electronic device, the electronic device can include artificial intelligence.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, a video, data, or the like can be displayed on a display portion. When the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission.

The electronic device of one embodiment of the present invention may include a sensor (a sensor having a function of measuring force, displacement, a position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, an electric field, current, voltage, electric power, radioactive rays, a flow rate, humidity, gradient, oscillation, a smell, or infrared rays).

The electronic device of one embodiment of the present invention can have a variety of functions. For example, the electronic device can have a function of displaying a variety of data (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of executing a variety of software (programs), a wireless communication function, and a function of reading out a program or data stored in a recording medium. FIG. 34 illustrates examples of the electronic device.

[Mobile Phone]

FIG. 34(A) illustrates a mobile phone (smartphone) which is a type of an information terminal. An information terminal 5500 includes a housing 5510 and a display portion 5511, and as input interfaces, a touch panel is provided in the display portion 5511 and a button is provided in the housing 5510.

The information terminal 5500 can execute an application utilizing artificial intelligence with the use of the chip of one embodiment of the present invention. Examples of the application utilizing artificial intelligence include an application for recognizing a conversation and displaying the contents of the conversation on the display portion 5511; an application for recognizing letters, figures, and the like input to the touch panel of the display portion 5511 by a user and displaying them on the display portion 5511; and an application for performing biometric authentication using fingerprints, voice prints, or the like.

[Information Terminal 1]

FIG. 34(B) illustrates a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

The desktop information terminal 5300 can execute an application utilizing artificial intelligence with the use of the chip of one embodiment of the present invention as the information terminal 5500 described above. Examples of the application utilizing artificial intelligence include design-support software, text correction software, and software for automatic menu generation. Furthermore, with the use of the desktop information terminal 5300, novel artificial intelligence can be developed.

Note that in the above description, although the smartphone and the desktop information terminal are respectively illustrated in FIGS. 34(A) and 34(B) as examples of the electronic device, one embodiment of the present invention can also be applied to an information terminal other than the smartphone and the desktop information terminal. Examples of an information terminal other than a smartphone and a desktop information terminal include a PDA (Personal Digital Assistant), a laptop information terminal, and a workstation.

[Electrical Appliance]

FIG. 34(C) illustrates an electric refrigerator-freezer 5800 which is an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

When the chip of one embodiment of the present invention is applied to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 including artificial intelligence can be obtained. Utilizing the artificial intelligence enables the electric refrigerator-freezer 5800 to have a function of automatically making a menu based on foods stored in the electric refrigerator-freezer 5800, expiration dates of the foods, or the like, a function of automatically adjusting the temperature to be appropriate for the foods stored in the electric refrigerator-freezer 5800, and the like.

Although the electric refrigerator-freezer is described as an electrical appliance in the example, other examples of the electrical appliance include a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating-cooling combination appliance such as an air conditioner, a washing machine, a drying machine, and an audio visual appliance.

[Game Console]

FIG. 34(D) illustrates a portable game console 5200 which is an example of a game console. The portable game console includes a housing 5201, a display portion 5202, a button 5203, and the like.

With the use of the GPU or the chip of one embodiment of the present invention in the portable game console 5200, the portable game console 5200 with low power consumption can be obtained. Furthermore, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.

Moreover, with the use of the GPU or the chip of one embodiment of the present invention in the portable game console 5200, the portable game console 5200 including artificial intelligence can be obtained.

Basically, the progress of a game, the actions and words of game characters, and expressions of a phenomenon or the like that occurs in the game are determined by a program of the game; however, the use of artificial intelligence in the portable game console 5200 enables expressions not limited by the program of the game. For example, expressions are possible in which questions posed by the player, the progress of the game, time, and the actions and words of game characters are changed.

When a game requiring a plurality of players is played on the portable game console 5200, the artificial intelligence can create a virtual game player; thus, the game can be played alone with the game player created by the artificial intelligence as an opponent.

Although the portable game console is illustrated in FIG. 34(D) as an example of a game machine, the game machine using the GPU or the chip of one embodiment of the present invention is not limited thereto. Examples of the game machine using the GPU or the chip of one embodiment of the present invention include a home stationary game machine, an arcade game machine installed in entertainment facilities (a game center, an amusement park, and the like), a throwing machine for batting practice installed in sports facilities, and the like.

[Moving Vehicle]

The GPU or the chip of one embodiment of the present invention can be used in an automobile, which is a moving vehicle, and around a driver's seat in the automobile.

FIG. 34(E1) illustrates an automobile 5700 which is an example of a moving vehicle, and FIG. 34(E2) illustrates the periphery of a windshield inside the automobile. FIG. 34(E2) illustrates a display panel 5701, a display panel 5702, and a display panel 5703 that are attached to a dashboard and a display panel 5704 that is attached to a pillar.

The display panel 5701 to the display panel 5703 can display a variety of kinds of information by displaying a speedometer, a tachometer, a mileage, a fuel meter, a gearshift indicator, air-condition setting, and the like. The content, layout, or the like of the display on the display panels can be changed appropriately to suit the user's preferences, so that the design can be improved. The display panel 5701 to the display panel 5703 can also be used as lighting devices.

The display panel 5704 displays an image taken by an imaging device (not illustrated) provided for the automobile 5700, whereby the view obstructed by the pillar (blind areas) can be complemented. That is, display of an image taken by an imaging device provided on the outside of the automobile 5700 can fill in blind areas and improve safety. In addition, display of an image that complements the area that cannot be seen makes it possible to confirm safety more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

Because the GPU or the chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used in an automatic driving system of the automobile 5700, for example. The chip can also be used for a system for navigation, risk prediction, or the like. The display panel 5701 to the display panel 5704 may display information regarding navigation, risk prediction, and the like.

Although an automobile is described above as an example of a moving vehicle, moving vehicles are not limited to an automobile. Examples of a moving vehicle include a train, a monorail train, a ship, and a flying object (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket), and these moving vehicles can include a system utilizing artificial intelligence when equipped with the chip of one embodiment of the present invention.

[Broadcasting System]

The GPU or the chip of one embodiment of the present invention can be used in a broadcasting system.

FIG. 34(F) schematically illustrates data transmission in a broadcasting system. Specifically, FIG. 34(F) illustrates a path in which a radio wave (a broadcasting signal) transmitted from a broadcast station 5680 reaches a television receiver (TV) 5600 of each household. The TV 5600 includes a receiving device (not illustrated), and the broadcast signal received by an antenna 5650 is transmitted to the TV 5600 through the receiving device.

Although an UHF (Ultra High Frequency) antenna is illustrated as the antenna 5650 in FIG. 34(F), a BS/110° CS antenna, a CS antenna, or the like can also be used as the antenna 5650.

A radio wave 5675A and a radio wave 5675B are broadcast signals for terrestrial broadcasting; a radio wave tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. Each household can view terrestrial TV broadcasting on the TV 5600 by receiving the radio wave 5675B with the antenna 5650. Note that the broadcasting system is not limited to the terrestrial broadcasting illustrated in FIG. 34(F) and may be satellite broadcasting using an artificial satellite, data broadcasting using an optical line, or the like.

The above-described broadcasting system may be a broadcasting system utilizing artificial intelligence by including the chip of one embodiment of the present invention. When the broadcast data is transmitted from the broadcast station 5680 to the TV 5600 of each household, the broadcast data is compressed by an encoder. The antenna 5650 receives the compressed broadcast data, and then the broadcast data is decompressed by a decoder of the receiving device in the TV 5600. Utilizing the artificial intelligence enables, for example, recognition of a display pattern included in a displayed image in motion compensation prediction, which is one of the compressing methods for the encoder. In addition, in-frame prediction or the like can also be performed utilizing the artificial intelligence. Furthermore, for example, when the broadcast data with low resolution is received and the broadcast data is displayed on the TV 5600 with high resolution, image interpolation processing such as upconversion can be performed in the broadcast data decompression by the decoder.

The above-described broadcasting system utilizing artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K and 8K) broadcasting, which needs a large amount of broadcast data.

As the application of artificial intelligence in the TV 5600, a recording device with artificial intelligence may be provided in the TV 5600, for example. With such a structure, the artificial intelligence can learn the user's preference, so that TV programs that suit the user's preference can be recorded automatically in the recording device.

The electronic device and the functions of the electronic device, the application example of the artificial intelligence and its effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device.

This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments, examples, and the like.

Example 1

In this example, the sheet resistance of a stack in which a conductor was provided over an oxide containing zinc was measured. A sheet resistance measurer whose measurement upper limit was 5.0×10⁶ Ω/sq. was used. Samples used for the measurement are described.

First, a method of fabricating Sample 1 is described. A surface of a substrate containing silicon was subjected to heat treatment in a hydrogen chloride (HCl) atmosphere, and a 100-nm-thick silicon oxide film was formed over the substrate. Next, a 300-nm-thick silicon oxynitride film was formed over the silicon oxide film by a CVD method. Oxygen was injected into the silicon oxynitride film by an ion implantation method such that the silicon oxynitride film functions as an oxygen supply film. Next, a 5-nm-thick first oxide was formed over the silicon oxynitride film, using a target with In:Ga:Zn=4:2:4.1 [atomic ratio], by a sputtering method. Then, a 5-nm-thick tantalum nitride film was formed over the first oxide by a sputtering method. The tantalum nitride film was formed using a target containing Ta in an atmosphere containing argon and nitrogen while the set temperature of the substrate was 200° C. Before the formation of the tantalum nitride film, heat treatment was performed under a reduced-pressure atmosphere for five minutes while the set temperature of the substrate was 200° C. The sheet resistance of Sample 1 obtained in this manner was 1.7×10³ Ω/sq.

Next, Sample 2 is described. Sample 2 was formed in such a manner that a tantalum nitride film was formed like Sample 1 and then heat treatment was performed at 400° C. in a nitrogen atmosphere for an hour. The sheet resistance of Sample 2 obtained in this manner was 3.9×10⁶ Ω/sq. It was found that heat treatment performed on the stack in which the tantalum nitride film was formed over the first oxide increases the sheet resistance by three or more digits, so that the sheet resistance was extremely high.

Next, Sample 3 is described. In Sample 3, the first oxide was formed as in Sample 1. Next, an oxide containing 1-nm-thick zinc was formed over the first oxide with the use of a target of zinc oxide. Next, a tantalum nitride film was formed over the oxide containing zinc, as in Sample 1. The sheet resistance of Sample 3 obtained in this manner was 1.2×10³ Ω/sq.

Next, Sample 4 is described. Sample 4 was formed in such a manner that after the tantalum nitride film was formed as in Sample 3, heat treatment was performed in a nitrogen atmosphere at a temperature of 400° C. for an hour. The sheet resistance of Sample 4 obtained in this manner was 2.4×10⁴ Ω/sq.

Next, Sample 5 is described. Sample 5 is different from Sample 4 described above in that the thickness of the oxide containing zinc was set to 3 nm. The sheet resistance of Sample 5 obtained in this manner was 6.5×10³ Ω/sq.

Next, Sample 6 is described. Sample 6 is different from Sample 4 described above in that the thickness of the oxide containing zinc was set to 5 nm. The sheet resistance of Sample 6 obtained in this manner was 3.8×10³ Ω/sq.

Next, Sample 7 is described. Sample 7 is different from Sample 4 in that a second oxide with a thickness of 5 nm was formed by a sputtering method using a target with In:Ga:Zn=1:1:1 [atomic ratio] instead of the first oxide. The sheet resistance of Sample 7 obtained in this manner was 2.9×10⁴ Ω/sq.

Next, Sample 8 is described. Sample 8 is different from Sample 7 described above in that the thickness of the oxide containing zinc was set to 3 nm. The sheet resistance of Sample 5 obtained in this manner was 8.6×10³ Ω/sq.

The above-described process conditions of Sample 1 to Sample 8 are listed in Table 1. FIG. 35 shows a graph of the sheet resistances of Sample 1 to Sample 8.

TABLE 1 Sample No. 1 2 3 4 5 6 7 8 Heat treatment No Yes No Yes Yes Yes Yes Yes Tantalum nitride film   5 nm Oxide containing zinc 1 nm 1 nm 3 nm 5 nm 1 nm 3 nm Second oxide 5 nm First oxide 5 nm Silicon oxynitride film 300 nm Silicon oxide film 100 nm

Comparison between Sample 1 and Sample 2 shows that the sheet resistance of the stack is significantly increased by heat treatment when the oxide containing zinc is not provided between the first oxide and the tantalum nitride film. On the other hand, comparison between Sample 3 and Sample 4 shows that an increase in the sheet resistance of the stack caused by heat treatment is inhibited when the oxide containing zinc is provided between the first oxide and the tantalum nitride film. Comparison between Sample 4 to Sample 6 shows that the larger the thickness of the oxide containing zinc becomes, the more the increase in the sheet resistance of the stack caused by heat treatment is inhibited. Comparison between Sample 4 and Sample 7 or comparison between Sample 5 and Sample 8 shows that the similar tendency of the sheet resistance of the stack is observed even when the compositions of the oxide are different. Comparison between Sample 7 and Sample 8 shows that also in the oxides with different compositions, the larger the thickness of the oxide containing zinc becomes, the more the increase in the sheet resistance of the stack caused by heat treatment is inhibited.

This embodiment can be implemented in an appropriate combination with the structures described in the other embodiments, the examples, and the like.

Example 2

In this example, results of measurement performed on a stack in which a conductor is provided over an oxide containing zinc will be described.

<Method of Fabricating Sample>

First, a method of fabricating samples (Sample 1A to Sample 1F and Sample 2A to Sample 2F) used for measurement is described.

In a common method of fabricating Sample 1A to Sample 1F and Sample 2A to Sample 2F, a surface of a substrate containing silicon is subjected to heat treatment in a hydrogen chloride (HCl) atmosphere, whereby a 100-nm-thick silicon oxide film was formed over the substrate. Next, a 300-nm-thick silicon oxynitride film was formed over the silicon oxide film by a CVD method. Furthermore, oxygen was implanted into the silicon oxynitride film by an ion implantation method so that the silicon oxynitride film functions as an oxygen supply film.

Next, in each of Sample 1A to Sample 1F, the first oxide with a thickness of 5 nm was formed over the silicon oxynitride film by a sputtering method. Note that the first oxide was formed under the following conditions: an In—Ga—Zn oxide target with In:Ga:Zn=1:1:1 [atomic ratio] was used; the oxygen gas flow rate was 45 sccm; the pressure was 0.7 Pa; a direct current power supply was used to apply a power of 500 W to the target side; and the substrate temperature was 200° C.

In each of Sample 2A to Sample 2F, the second oxide with a thickness of 5 nm was formed over the silicon oxynitride film by a sputtering method. Note that the second oxide was formed under the following conditions: an In—Ga—Zn oxide target with In:Ga:Zn=4:2:4.1 [atomic ratio] was used; the argon gas flow rate was 30 sccm; the oxygen gas flow rate was 15 sccm; the pressure was 0.7 Pa; a direct current power supply was used to apply a power of 500 W to the target side; and the substrate temperature was 200° C.

Next, in each of Sample 1C to Sample 1F, the oxide containing zinc was formed over the first oxide by a sputtering method while the thicknesses of the oxides were different. In each of Sample 2A to Sample 2F, the oxide containing zinc was formed over the second oxide by a sputtering method while the thicknesses of the oxides were different. The second oxide was formed under the following conditions: a zinc oxide target with Zn: 0=1:1 [atomic ratio] was used; the argon gas flow rate was 25 sccm; the oxygen gas flow rate was 25 sccm; the pressure was 0.7 Pa; a direct current power supply was used to apply a power of 200 W to the target side; and the substrate temperature was 200° C.

In Sample 1C, Sample 1D, Sample 2A, and Sample 2B, the thickness of the oxide containing zinc was set to 1 nm. In Sample 1E, Sample 1F, Sample 2C, and Sample 2D, the thickness of the oxide containing zinc was set to 3 nm. In Sample 2E and Sample 2F, the thickness of the oxide containing zinc was set to 5 nm.

Next, in Sample 1A and Sample 1B, a tantalum nitride film with a thickness of 5 nm was formed over the first oxide by a sputtering method. In Sample 1C to Sample 1F and Sample 2A to Sample 2F, a tantalum nitride film with a thickness of 5 nm was formed over the oxide containing zinc by a sputtering method. The tantalum nitride film was formed under the following conditions: a target containing tantalum was used; the argon gas flow rate was 50 sccm; the nitrogen gas flow rate was 10 sccm; the pressure was 0.6 Pa; the direct current power supply was 1 kW; and the substrate temperature was room temperature.

Next, Sample 1B, Sample 1D, Sample 1F, Sample 2B, Sample 2D, and Sample 2F were subjected to heat treatment. The heat treatment was performed at 400° C. in an atmosphere containing nitrogen for an hour.

Through the above steps, Sample 1A to Sample 1F and Sample 2A to Sample 2F were fabricated. Table 2 shows the process conditions of the samples.

TABLE 2 Sample No. 1A 1B 1C 1D 1E 1F 2A 2B 2C 2D 2E 2F Heat treatment No Yes No Yes No Yes No Yes No Yes No Yes Tantalum nitride film   5 nm Oxide containing zinc 1 nm 3 nm 1 nm 3 nm 5 nm Second oxide 5 nm First oxide 5 nm Silicon oxynitride film 300 nm Silicon oxide film 100 nm

<Cross-Sectional TEM and Nanobeam Electron Diffraction>

Cross-sectional TEM images of Sample 1A to Sample 1F and Sample 2A to Sample 2F were taken in a Cs-TEM mode with JEM-ARM200F manufactured by JEOL Ltd. at an accelerating voltage of 200 kV. FIG. 36 and FIG. 37 show results of the cross-sectional TEM images that were taken. FIGS. 36(A) and 36(B) are cross-sectional TEM images of a region including the first oxide and the tantalum nitride film in Sample 1A and Sample 1B, respectively. FIGS. 36(C), 36(D), 36(E), and 36(F) are cross-sectional TEM images of a region including the first oxide, the oxide containing zinc, and the tantalum nitride film in Sample 1C, Sample 1D, Sample 1E, and Sample 1F, respectively. FIGS. 37(A), 37(B), 37(C), 37(D), 37(E), and 37(F) are cross-sectional TEM images of a region including the second oxide, the oxide containing zinc, and the tantalum nitride film in Sample 2A, Sample 2B, Sample 2C, Sample 2D, Sample 2E, and Sample 2F, respectively.

Note that in each of Sample 1E, Sample 1F, Sample 2C, and Sample 2D, an electron diffraction pattern of a region denoted by a circle was obtained by nanobeam electron diffraction with a beam diameter of approximately 1 nmϕ. The electron diffraction patterns of Sample 1E, Sample 1F, Sample 2C, and Sample 2D are shown in lower right portions of FIGS. 36(E), 36(F), 37(C), and 37(D), respectively.

In FIGS. 36(C) to 36(F) and FIGS. 37(A) to 37(F), a different layer was not observed in the vicinity of an interface between the oxide containing zinc and the tantalum nitride film. According to the electron diffraction patterns of FIGS. 36(E) and 36(F), the oxide containing zinc formed over the first oxide has a hexagonal crystal structure. In addition, according to the electron diffraction patterns of FIGS. 37(C) and 37(D), the oxide containing zinc formed over the second oxide has a hexagonal crystal structure. Note that a difference was not observed between the crystal structures of the oxide containing zinc in the samples not subjected to heat treatment and the crystal structures of the oxide containing zinc in the samples subjected to heat treatment.

<EDX Analysis>

Next, Sample 1A to Sample 1F and Sample 2A to Sample 2F were subjected to elementary analysis with EDX. Note that as an apparatus for cross-sectional observation and EDX measurement, JEM-ARM200F manufactured by JEOL Ltd. was used, and as an elementary analysis apparatus, an energy dispersive X-ray spectrometer JED-2300T manufactured by JEOL Ltd. was used. The cross-sectional TEM images were taken in a Cs-TEM mode at an accelerating voltage of 200 kV. A Si drift detector was used to detect an X-ray emitted from the samples.

In the EDX measurement, measurement points in analysis target regions of samples were subjected to electron beam irradiation with a beam diameter of approximately 0.2 nmϕ, and the energy of characteristic X-ray of the sample generated by the irradiation and its frequency were measured, whereby the EDX spectra corresponding to the points were obtained. In this example, peaks of EDX spectra of the points were attributed to electron transition to the L shell in an In atom, electron transition to the K shell in a Ga atom, electron transition to the K shell in a Zn atom, and the K shell in an O atom, whereby an EDX map of each element was obtained. Next, in a direction perpendicular to the substrate surface of the sample (the depth direction), an EDX map with a width of 20 nm in a direction parallel to the substrate surface of the sample was extracted, whereby the proportion of each element in the depth direction can be calculated.

FIG. 38 and FIG. 39 each show a superposition of the cross-sectional TEM image of the region subjected to the elementary analysis and the proportions of elements in the depth direction. FIGS. 38(A), 38(B), 38(C), 38(D), 38(E), and 38(F) show the cross-sectional TEM images and the proportions of elements in the depth direction in Sample 1A, Sample 1B, Sample 1C, Sample 1D, Sample 1E, and Sample 1F, respectively. FIGS. 39(A), 39(B), 39(C), 39(D), 39(E), and 39(F) show the cross-sectional TEM images and the proportions of elements in the depth direction in Sample 2A, Sample 2B, Sample 2C, Sample 2D, Sample 2E, and Sample 2F, respectively.

The solid line in each of the cross-sectional TEM images in FIG. 38 and FIG. 39 represents the proportions of elements in the depth direction. Four solid lines in each of FIGS. 38(A) to 38(F) and FIGS. 39(A) to 39(F) represent the proportions of O atoms, Zn atoms, Ga atoms, and In atoms in the depth direction, respectively, from the left. The proportion of each element is shown in a direction parallel to a substrate surface of the sample, and the proportion of the element is higher toward the left side. The unit of the element proportion is arbitrary. To make the proportions of elements in the depth direction more visible, a solid line showing the proportion of each element in the depth direction is shifted in the direction parallel to the substrate surface of the sample.

The dotted line in each of the cross-sectional TEM images in FIG. 38 and FIG. 39 indicates an interface between the first oxide and the tantalum nitride film, an interface between the oxide containing zinc and the tantalum nitride film, an interface between the oxide containing zinc and the first oxide, or an interface between the oxide containing zinc and the second oxide. The dashed-dotted line in each of FIGS. 38(B), 38(D), 38(F), 39(B), 39(D), and 39(F) indicates the depth at which the proportion of O atoms is half the peak value.

It was found from FIGS. 38(A) and 38(B) that the tantalum nitride film on the first oxide side was oxidized by approximately 2.3 nm by the heat treatment. It was found from FIGS. 38(C) to 38(F) and FIGS. 39(A) to 39(F) that the tantalum nitride film on the oxide containing zinc side was oxidized by a width from 1.2 nm to 1.3 nm by the heat treatment. In view of the above, providing the oxide containing zinc between the first oxide or the second oxide and the tantalum nitride film can inhibit diffusion of oxygen from the first oxide or the second oxide to the tantalum nitride film, which is caused by heat treatment, so that oxidation of the tantalum nitride film can be prevented.

<XPS Analysis 1>

Sample 1A to Sample 1F and Sample 2A to Sample 2F were subjected to X-ray photoelectron spectroscopy (XPS) measurement. For the XPS measurement, Quantera II manufactured by PHI, Inc. was used. Monochromatic Al Kα ray (1486.6 eV) was used as an X-ray source. A detection area was set to 100 μmϕ. An extraction angle was set to 90°. The detection depth is estimated to be approximately 8 nm. In the XPS measurement, the bond state of the sample from a surface to the detection depth can be evaluated.

FIG. 40 shows the XPS measurement results of Sample 1A to Sample 1F and Sample 2A to Sample 2F. FIG. 40(A) shows the XPS measurement results of the samples not subjected to heat treatment (Sample 1A, Sample 1C, Sample 1E, Sample 2A, Sample 2C, and Sample 2E), and FIG. 40(B) shows the XPS measurement results of the samples subjected to heat treatment (Sample 1B, Sample 1D, Sample 1F, Sample 2B, Sample 2D, and Sample 2F). The vertical axis in FIG. 40 shows the proportions of tantalum oxide, tantalum oxynitride, and tantalum oxynitride containing less tantalum nitride or oxygen, which are contained in the tantalum nitride film.

According to FIG. 40, the proportion of tantalum oxynitride after the heat treatment is increased. Therefore, the tantalum nitride film is oxidized by the heat treatment. As the thickness of the oxide containing zinc increases, an increase in the proportion of tantalum oxynitride after the heat treatment is reduced. This shows that oxidation of the tantalum nitride film by heat treatment can be more inhibited as the thickness of the oxide containing zinc is increased. Furthermore, in the samples including the second oxide film, the proportion of tantalum oxynitride after the heat treatment is low as compared with the samples including the first oxide; thus, oxidation of the tantalum nitride film is slightly inhibited.

<XPS Analysis 2>

XPS measurement of Sample 2E and Sample 2F was combined with sputtering, so that analysis in the depth direction was performed. Specifically, the XPS measurement in the depth direction was performed in such a manner that argon ions were deposited to 1 nm to 2 nm from the surfaces of Sample 2E and Sample 2F by sputtering.

FIG. 41(A) shows a spectrum of Zn3p obtained by the XPS measurement of Sample 2E and Sample 2F. The dotted line in FIG. 41(A) shows a spectrum of Sample 2E and the solid line in FIG. 41(A) shows a spectrum of Sample 2F. In FIG. 41(A), the horizontal axis represents binding energy [eV] and the vertical axis represents intensity [arbitary unit (a.u.)] of photoelectrons. A peak of binding energy that appears near 498 eV is derived from zinc oxide. Thus, the larger the number of zinc-oxide bond states in the oxide containing zinc is, the higher the intensity of the peak is. A peak of binding energy that appears near 495 eV is derived from zinc. Thus, the larger the number of zinc bond states in the oxide containing zinc is, the higher the intensity of the peak is.

FIG. 41(B) shows the results of XPS measurement of Sample 2E and Sample 2F. The vertical axis in FIG. 41(B) represents the proportions of zinc oxide and zinc contained in the oxide containing zinc.

In FIG. 41, a bond state derived from zinc is observed in Sample 2E. Moreover, in Sample 2F, the proportion of zinc is decreased and the proportion of zinc oxide is increased. Therefore, it is found that zinc contained in the oxide containing zinc is oxidized by heat treatment.

This embodiment can be implemented in an appropriate combination with the structures described in the other embodiments, the examples, and the like.

REFERENCE NUMERALS

200: transistor, 205: conductor, 205 a: conductor, 205 b: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 218: conductor, 222: insulator, 224: insulator, 224A: insulating film, 230: oxide, 230 a: oxide, 230A: oxide film, 230 b: oxide, 230B: oxide film, 230 c: oxide, 230C: oxide film, 231 a: region, 231 b: region, 234: region, 240: conductor, 240 a: conductor, 240 b: conductor, 241: insulator, 241 a: insulator, 241 b: insulator, 242: conductor, 242 a: conductor, 242A: conductive film, 242 b: conductor, 242B: conductor layer, 243: oxide, 243 a: oxide, 243A: oxide film, 243 b: oxide, 243B: oxide layer, 245: conductor, 246: conductor, 246 a: conductor, 246 b: conductor, 250: insulator, 250A: insulating film, 260: conductor, 260 a: conductor, 260Aa: conductive film, 260Ab: conductive film, 260 b: conductor, 265: dummy film, 265A: dummy film, 272: insulator, 272A: insulating film, 273: insulator, 273A: insulating film, 274: insulator, 276: insulator, 280: insulator, 281: insulator, 282: insulator. 

1. A semiconductor device comprising: a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a first conductor over the third oxide, the first conductor functioning as one of a source electrode and a drain electrode; a second conductor over the fourth oxide, the second conductor functioning as the other of the source electrode and the drain electrode; a fifth oxide over the second oxide; a second insulator over the fifth oxide, the second insulator functioning as a gate insulator; and a third conductor over the second insulator, the third conductor functioning as a gate electrode, wherein the fifth oxide is in contact with a side surface of the third oxide and a side surface of the fourth oxide, wherein a conductivity of the third oxide is higher than a conductivity of the second oxide, wherein a conductivity of the fourth oxide is higher than a conductivity of the second oxide, wherein the second oxide comprises In, an element M, and Zn, wherein the element M is A1, Ga, Y, or Sn, and wherein each of the third oxide and the fourth oxide comprises Zn.
 2. The semiconductor device according to claim 1, wherein the third oxide comprises a first region not overlapping with the first conductor, wherein the fourth oxide comprises a second region not overlapping with the second conductor, and wherein the fifth oxide is in contact with a top surface of the first region and a top surface of the second region.
 3. A semiconductor device comprising: a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a first conductor over the third oxide, the first conductor functioning as one of a source electrode and a drain electrode; a second conductor over the fourth oxide, the second conductor functioning as the other of the source electrode and the drain electrode; a fifth oxide over the second oxide; a second insulator over the fifth oxide, the second insulator functioning as a gate insulator; and a third conductor over the second insulator, the third conductor functioning as a gate electrode, wherein the fifth oxide is in contact with a side surface of the third oxide and a side surface of the fourth oxide, wherein a conductivity of the third oxide is higher than a conductivity of the second oxide, and wherein a conductivity of the fourth oxide is higher than a conductivity of the second oxide.
 4. The semiconductor device according to claim 1, wherein the third oxide comprises a first region not overlapping with the first conductor, wherein the fourth oxide comprises a second region not overlapping with the second conductor, and wherein the fifth oxide is in contact with a top surface of the first region and a top surface of the second region.
 5. (canceled)
 6. The semiconductor device according to claim 1, wherein a thickness of each of the third oxide and the fourth oxide is greater than or equal to 1 nm and less than or equal to 10 nm.
 7. (canceled)
 8. The semiconductor device according to claim 1, wherein each of the third oxide and the fourth oxide has crystallinity.
 9. (canceled)
 10. The semiconductor device according to claim 1, wherein the fifth oxide, the second insulator, and the third conductor are positioned between the third oxide and the fourth oxide.
 11. The semiconductor device according to claim 3, wherein a thickness of each of the third oxide and the fourth oxide is greater than or equal to 1 nm and less than or equal to 10 nm.
 12. The semiconductor device according to claim 3, wherein each of the third oxide and the fourth oxide has crystallinity.
 13. The semiconductor device according to claim 3, wherein the fifth oxide, the second insulator, and the third conductor are positioned between the third oxide and the fourth oxide.
 14. A semiconductor device comprising: a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a first conductor over the third oxide, the first conductor functioning as one of a source electrode and a drain electrode; a second conductor over the fourth oxide, the second conductor functioning as the other of the source electrode and the drain electrode; a fifth oxide over the second oxide; a second insulator over the fifth oxide, the second insulator functioning as a gate insulator; and a third conductor over the second insulator, the third conductor functioning as a gate electrode, wherein the fifth oxide is in contact with a side surface of the third oxide and a side surface of the fourth oxide, wherein the second oxide comprises In, an element M, and Zn, wherein the element M is Al, Ga, Y, or Sn, and wherein each of the third oxide and the fourth oxide comprises Zn.
 15. The semiconductor device according to claim 14, wherein the third oxide comprises a first region not overlapping with the first conductor, wherein the fourth oxide comprises a second region not overlapping with the second conductor, and wherein the fifth oxide is in contact with a top surface of the first region and a top surface of the second region.
 16. The semiconductor device according to claim 14, wherein a thickness of each of the third oxide and the fourth oxide is greater than or equal to 1 nm and less than or equal to 10 nm.
 17. The semiconductor device according to claim 14, wherein each of the third oxide and the fourth oxide has crystallinity.
 18. The semiconductor device according to claim 14, wherein the fifth oxide, the second insulator, and the third conductor are positioned between the third oxide and the fourth oxide. 